Light emitting diode structure

• US 8,552,436 B2
• Filed: 12/07/2012
• Issued: 10/08/2013
• Est. Priority Date: 11/18/2011
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: LuxVue Techonology Corporation (Apple Inc.)
• Inventors: Bibl, Andreas, Higginson, John A., Law, Hung-Fai Stephen, Hu, Hsin-Hua
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): Singh, Harpreet
• Application Number:
  US13/708,695
• Publication Number:
  US 20130126827A1
• Time in Patent Office: 305 Days
• Field of Search: None
• US Class Current: 257/81
• CPC Class Codes: F21V 7/00 Reflectors for light sources characterised by cooling arrangements F21V29/505
• CPC Class Codes: H01L 2224/95 at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 27/15 including semiconductor components having potential barriers, specially adapted for light emission
• CPC Class Codes: H01L 29/0684 characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/04 with a quantum effect structure or superlattice, e.g. tunnel junction
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/28 containing only elements of Group II and Group VI of the Periodic Table
• CPC Class Codes: H01L 33/30 containing only elements of Group III and Group V of the Periodic Table

Abstract

A micro light emitting diode (LED) and a method of forming an array of micro LEDs for transfer to a receiving substrate are described. The micro LED structure may include a micro p-n diode and a metallization layer, with the metallization layer between the micro p-n diode and a bonding layer. A conformal dielectric barrier layer may span sidewalls of the micro p-n diode. The micro LED structure and micro LED array may be picked up and transferred to a receiving substrate.

Claims

1. A structure comprising:

a substrate layer;

an array of posts, wherein each of the posts has a height between 0.2-4 μ

m, and the array of posts and the substrate layer are integrally formed from a single piece of material comprising a polymer material;

a corresponding array of laterally separate metallization layers directly over the array of posts; and

a semiconductor device layer directly over the array of laterally separate metallization layers, wherein the semiconductor device layer has a uniform thickness across the substrate layer.

2. The structure of claim 1, wherein each of the laterally separate metallization layers has a width of 1-100 μ

m scale.

3. The structure of claim 2, wherein each of the posts has a width of 1-100 μ

m scale.

4. The structure of claim 1, wherein the semiconductor device layer is a p-n diode layer.

5. The structure of claim 4, wherein the p-n diode layer includes a p-doped layer, an n-doped layer, and a quantum well layer between the p-doped layer and the n-doped layer.

6. The structure of claim 5, wherein quantum well layer is a multiple quantum well configuration.

7. The structure of claim 5, wherein each of the laterally separate metallization layers makes ohmic contact with the p-n diode layer.

8. The structure of claim 5, wherein each of the laterally separate metallization layers is reflective to light emission.

9. The structure of claim 5, wherein each of the laterally separate metallization layers has a thickness of 0.1-2 μ

m.

10. The structure of claim 5, wherein the quantum well layer has a thickness of less than approximately 0.3 μ

m.

11. The structure of claim 5, wherein the p-doped layer has a thickness of approximately 0.1-1 μ

m.

12. The structure of claim 5, wherein the n-doped layer has a thickness of approximately 0.1-6 μ

m.

13. The structure of claim 5, wherein the p-n diode layer has a thickness of less than approximately 9.3 μ

m.

14. The structure of claim 1, further comprising an array of laterally separate bonding layers between the array of posts and the array of laterally separate metallization layers.

15. The structure of claim 14, wherein array of laterally separate bonding layers is formed of a metal or metal alloy.

16. The structure of claim 15, wherein the array of laterally separate bonding layers is in direct contact with the array of posts and the array of laterally separate metallization layers.

17. The structure of claim 3, comprising millions of posts in the array of posts.

18. The structure of claim 3, comprising hundreds of millions of posts in the array of posts.

19. The structure of claim 1, wherein the semiconductor device layer is designed to perform an electronic function.

20. The structure of claim 19, wherein the semiconductor device layer comprises a device selected from the group consisting of a diode, transistor, and integrated circuit.

21. The structure of claim 1, wherein the semiconductor device layer is designed to perform a photonic function.

22. The structure of claim 21, wherein the semiconductor device layer comprises a device selected from the group consisting of a light emitting diode and laser.

23. The structure of claim 2, wherein each metallization layer includes a bottom surface that is wider than a corresponding post top surface directly underneath the metallization layer.

24. The structure of claim 23, wherein the semiconductor device layer is a p-n diode layer that includes a p-doped layer, an n-doped layer, and a quantum well layer between the p-doped layer and the n-doped layer.

25. The structure of claim 24, wherein each of the laterally separate metallization layers makes ohmic contact with the p-n diode layer.

26. The structure of claim 25, wherein each of the laterally separate metallization layers comprises an electrode layer that makes ohmic contact with the p-n diode layer, and a barrier layer between the ohmic layer and a corresponding post directly underneath the metallization layer.