Segmented pillar layout for a high-voltage vertical transistor

• US 8,552,493 B2
• Filed: 06/02/2009
• Issued: 10/08/2013
• Est. Priority Date: 02/16/2007
• Status: Expired due to Fees

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Parthasarathy, Vijay, Grabowski, Wayne Bryan
• Primary Examiner(s): PIZARRO CRESPO, MARCOS D
• Application Number:
  US12/455,462
• Publication Number:
  US 20090273023A1
• Time in Patent Office: 1,589 Days
• Field of Search: 257328-342, 257/488, 257/E29.26, 257/E29.262
• US Class Current: 257/331
• CPC Class Codes: H01L 21/77 Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate electrically programmable read-only memories or multistep manufacturing processes therefor H10B69/00
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0607 for preventing surface leakage or controlling electric field concentration
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged.

Claims

1. An apparatus comprising:

a plurality of transistor segments arranged on a die, each transistor segment having an elongated annular shape with a length elongated in a first lateral direction and a width in a second lateral direction, each transistor segment including;

a pillar of a semiconductor material, the pillar including a drift region that extends in a vertical direction through the die;

a first and second dielectric regions disposed on opposite sides of the pillar, respectively, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar;

first and second field plates respectively disposed in the and second dielectric regions;

wherein the transistor segments are arranged into a plurality of sections, a first section comprising a first row of transistor segments arranged in a side-by-side relationship in the second lateral direction with the second dielectric region of each transistor segment of the first section being merged, a second section comprising a second row of transistor segments arranged in the side-by-side relationship in the second lateral direction with the second dielectric region of each transistor segment of the second section being merged, the merged second dielectric region of the first section being separated from the merged second dielectric region of the second section in the first lateral direction by a dummy pillar of the semiconductor material, the dummy pillar having a width in the first lateral direction that is substantially smaller than the length of each transistor segment.

2. The apparatus of claim 1 wherein the first and second sections each extend in the second lateral direction substantially across a width of the die, the first section and the second section additively extending in the first lateral direction substantially across a length of the die.

3. The apparatus of claim 1 wherein the pitch and a length in the second lateral direction of the dummy pillar are sufficiently sized to relieve mechanical stress induced by the first and second dielectric regions disposed on opposite sides of the pillar of each transistor segment.

4. The apparatus of claim 1 wherein the pitch and a length in the second lateral direction of the dummy pillar are sufficiently sized to relieve mechanical stress induced by the first and second dielectric regions disposed on opposite sides of the pillar of each transistor segment.

5. The apparatus of claim 1 wherein the pillar further comprises a source region disposed near a top surface of the die, and a body region that vertically separates the source region from the extended drain region.

6. The apparatus of claim 5 further comprising a gate disposed within the first and second dielectric regions adjacent the body region, the gate being insulated from the body region and the first and second field plates.