Self-aligned semiconductor trench structures

• US 8,552,526 B2
• Filed: 12/21/2012
• Issued: 10/08/2013
• Est. Priority Date: 09/11/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Juengling, Werner, Lane, Richard
• Primary Examiner(s): Lee, Calvin
• Assistant Examiner(s): Harrison, Monica D
• Application Number:
  US13/725,384
• Publication Number:
  US 20130113069A1
• Time in Patent Office: 291 Days
• Field of Search: 257/510
• US Class Current: 257/510
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/3088 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H10B 12/0387 Making the trench

Abstract

Methods for forming a semiconductor device include forming self-aligned trenches, in which a first set of trenches is used to align a second set of trenches. Methods taught herein can be used as a pitch doubling technique, and may therefore enhance device integration. Further, employing a very thin CMP stop layer, and recessing surrounding materials by about an equal amount to the thickness of the CMP stop layer, provides improved planarity at the surface of the device.

Claims

1. A semiconductor structure comprising:

a semiconductor substrate;

a plurality of first trenches extending parallel to one another in a first direction, the first trenches extending into the substrate to a first trench depth and having first trench sidewalls, wherein each of the first trench sidewalls are lined with a first liner;

a plurality of second trenches extending substantially parallel to the first trenches and alternating with the first trenches, the second trenches extending into the substrate to a second trench depth greater than the first trench depth and having second trench sidewalls, wherein each of the second trench sidewalls are lined with a plurality of second liners; and

a plurality of inter-trench regions disposed between alternating first trenches and second trenches.

2. The semiconductor structure as in claim 1, wherein the first liner comprises an oxide liner.

3. The semiconductor structure as in claim 2, wherein the second liners comprise a barrier liner.

4. The semiconductor structure as in claim 3, wherein the barrier liner comprises a silicon nitride layer.

5. The semiconductor structure as in claim 1, wherein the second liners comprise an oxide liner and a silicon nitride liner.

6. The semiconductor structure as in claim 5, wherein the oxide liner is in contact with the second trench sidewalls and the silicon nitride liner is in contact with the oxide liner.

7. The semiconductor structure as in claim 5, wherein the second liners further comprise a second oxide liner.

8. The semiconductor structure as in claim 1, wherein the first trench depth is between about 2700 Å

and 3300 Å

.

9. The semiconductor structure as in claim 1, wherein a width of the first trench is between about 170 Å

and 430 Å

.

10. The semiconductor structure as in claim 1, wherein the second trench depth is between about 4500 Å

and 5500 Å

.

11. The semiconductor structure as in claim 1, wherein a width of the second trench is between about 170 Å

and 430 Å

12. The semiconductor structure as in claim 1, wherein the first trenches are filled with a first filler material and the second trenches are filled with a second filler material.

13. The semiconductor structure as in claim 12, wherein each of the first trenches have a first filler surface region and a first liner surface region and each of the second trenches have a second filler surface region and a second liner surface region, and wherein at least a portion of the first filler surface region and at least a portion of the second filler surface region form a substantially coplanar surface.

14. The semiconductor structure as in claim 13 wherein at least a portion of the second liner surface region protrudes above the second filler surface region.

15. The semiconductor structure as in claim 12, wherein the second filler material is a spin-on dielectric.

16. The semiconductor structure as in claim 12, wherein the first filler material is a high density plasma oxide.

17. A semiconductor structure comprising:

a semiconductor substrate;

a plurality of first trenches extending along a first direction and etched into the substrate to a first depth, the first trenches lined with a first liner and filled with a first filler material, wherein each of the first trenches have a first filler surface region and a first liner surface region;

a plurality of second trenches extending substantially parallel to the first trenches and alternating with the first trenches, the second trenches etched into the substrate to a second depth greater than the first depth, the second trenches lined with a plurality of second liners and filled with a second filler material, wherein each of the second trenches have a second filler surface region and a second liner surface region;

a plurality of inter-trench regions disposed between alternating first trenches and second trenches, the inter-trench region having an inter-trench surface; and

wherein at least a portion of the second liner surface region is selectively recessed below the inter-trench surface.

18. The semiconductor structure as in claim 17, wherein the second liners comprise an oxide liner and a silicon nitride liner.

19. The semiconductor structure as in claim 18, further comprising a second oxide liner.

20. The semiconductor structure as in claim 17, wherein at least a portion of the second liner surface region is substantially co-planar with the inter-trench surface.

21. The semiconductor structure as in claim 17, wherein the second filler surface region is substantially recessed from the inter-trench surface.

22. The semiconductor structure as in claim 17, wherein the second filler surface region is substantially recessed from at least a portion of the second liner surface region.

23. A semiconductor structure comprising:

a semiconductor substrate;

a pair of adjacent semiconductor walls disposed on the substrate, each wall having a top surface, a short side, and a long side;

a shallow trench extending along a first direction and disposed between the semiconductor walls, the shallow trench having a shallow trench depth and shallow trench sidewalls, wherein the shallow trench sidewalls are formed by the two short sides of the pair of adjacent semiconductor walls and are lined with a first liner; and

a pair of deep trenches extending parallel to the shallow trench, each deep trench disposed adjacent to one of the semiconductor walls on the long side, each of the deep trenches having a deep trench depth and deep trench sidewalls, wherein one of the deep trench sidewalls is formed by a long side of one of the semiconductor walls, wherein the second trench depth is greater than the first trench depth, and wherein the deep trench sidewalls are lined with a plurality of second liners.

24. The semiconductor structure as in claim 23, wherein the shallow trench has a first filler surface region and a first liner surface region and the deep trench has a second filler surface region and a second liner surface region, and wherein at least a portion of the first filler surface region and at least a portion of the second filler surface region form a substantially coplanar surface.

25. The semiconductor structure as in claim 23, wherein at least a portion of the first filler surface region is vertically positioned below the top surface.