Conductive pad on protruding through electrode semiconductor device

• US 8,552,548 B1
• Filed: 11/29/2011
• Issued: 10/08/2013
• Est. Priority Date: 11/29/2011
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Do, Won Chul, Ko, Yong Jae
• Primary Examiner(s): LE, DUNG ANH
• Application Number:
  US13/306,685
• Time in Patent Office: 679 Days
• Field of Search: 257/621, 257/686, 257/698, 257773-774, 257/742, 257/778
• US Class Current: 257/698
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2224/03002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/03464 Electroless plating
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05026 the internal layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/05083 Three-layer arrangements
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05164 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05562 On the entire exposed surface of the internal layer
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05583 Three-layer coating
• CPC Class Codes: H01L 2224/05644 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/06181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/12105 : Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13022 : the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13025 : the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13082 : Two-layer arrangements
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13124 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13184 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 23/3192 : Multilayer coating
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]

Abstract

To form a semiconductor device, a through electrode is formed in a semiconductor die, and a dielectric layer is then formed to cover the through electrode. The dielectric layer has an opening by being partially etched to allow the through electrode to protrude to the outside, or has a thickness thinner overall so as to allow the through electrode to protrude to the outside. Subsequently, a conductive pad is formed on the through electrode protruding to the outside through the dielectric layer by using an electroless plating method.

Claims

1. A semiconductor device comprising:

a semiconductor die comprising;

a first surface;

a second surface opposing the first surface; and

a through hole penetrating the first surface and the second surface;

a through electrode in the through hole and penetrating the first surface and the second surface;

a dielectric layer coupled to the first surface of the semiconductor die, the through electrode penetrating and directly contacting the dielectric layer; and

a conductive pad directly contacting an exposed top surface and an exposed sidewall of the through electrode.

2. The semiconductor device as claimed in claim 1 wherein a top surface of the dielectric layer and the top surface of the through electrode are in the same plane.

3. The semiconductor device as claimed in claim 1, wherein the dielectric layer comprises an opening corresponding to the through electrode.

4. The semiconductor device as claimed in claim 1, wherein the dielectric layer comprises a protrusion corresponding to the through electrode.

7. The semiconductor device as claimed in claim 1, wherein an insulating layer is between the through electrode and the semiconductor die.

10. The semiconductor device as claimed in claim 1, wherein the semiconductor die further includes:

an active region coupled to the through electrode;

a bond pad coupled to the active region; and

a conductive bump coupled to the bond pad.

11. The semiconductor device as claimed in claim 10, further comprising a solder cap coupled to the conductive bump.

12. The semiconductor device as claimed in claim 10 further comprising

an insulating layer, wherein the conductive bump, the solder cap, and the insulating layer are coupled to a carrier wafer by a temporary bonding adhesive.

5. A semiconductor device comprising:

a semiconductor die comprising;

a first surface;

a second surface opposing the first surface; and

a through hole penetrating the first surface and the second surface;

a through electrode in the through hole and penetrating the first surface and the second surface;

a dielectric layer coupled to the first surface of the semiconductor die, the through electrode penetrating the dielectric layer; and

a conductive pad coupled to the through electrode, wherein the conductive pad comprises;

a first electroless plating layer coupled to the through electrode; and

a second electroless plating layer coupled to the first electroless plating layer.

6. The semiconductor device as claimed in claim 5, wherein the first electroless plating layer comprises nickel, and the second electroless plating layer comprises gold.

8. The semiconductor device as claimed in claim 5, wherein an insulating layer is between the through electrode and the dielectric layer.

9. The semiconductor device as claimed in claim 5, wherein the conductive pad is coupled to only a top surface of the through electrode.

13. A semiconductor device comprising:

a semiconductor die comprising;

a first surface;

a second surface opposing the first surface; and

a through hole penetrating the first surface and the second surface;

a through electrode in the through hole and penetrating the first surface and the second surface;

a dielectric layer coupled to the first surface of the semiconductor die, wherein the dielectric layer comprises an opening extending partially into the dielectric layer such that the first surface of the semiconductor die is not exposed through the opening, the through electrode penetrating the dielectric layer, wherein the through electrode comprises an exposed top surface and exposed sidewall exposed through the opening; and

a conductive pad coupled to the exposed top surface and the exposed sidewall, the conductive pad comprising;

a first layer coupled to the exposed top surface and the exposed sidewall;

a second layer coupled to the first layer; and

a third layer coupled to the second layer.

14. A semiconductor device comprising:

a semiconductor die comprising;

a first surface; and

a second surface opposing the first surface;

a through electrode penetrating the first surface and the second surface;

a dielectric layer coupled to the first surface of the semiconductor die, the through electrode penetrating and directly contacting the dielectric layer; and

a conductive pad directly contacting an exposed top surface and an exposed sidewall of the through electrode.

15. The semiconductor device as claimed in claim 14, wherein the dielectric layer comprises an opening corresponding to the through electrode.

16. The semiconductor device as claimed in claim 14, wherein the dielectric layer comprises a protrusion corresponding to the through electrode.

17. A semiconductor device comprising:

a semiconductor die comprising;

a first surface; and

a second surface opposing the first surface;

a through electrode penetrating the first surface and the second surface;

an insulating layer between the through electrode and the semiconductor die;

a dielectric layer coupled to the first surface of the semiconductor die, the through electrode penetrating and directly contacting the dielectric layer; and

a conductive pad directly contacting an exposed top surface and an exposed sidewall of the through electrode.