Semiconductor device

• US 8,552,553 B2
• Filed: 05/28/2010
• Issued: 10/08/2013
• Est. Priority Date: 10/14/2009
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Lo, Jian-Wen, Chen, Chien-Fan
• Primary Examiner(s): Nguyen, Ha Tran T
• Assistant Examiner(s): DEHNE, AARON A
• Application Number:
  US12/790,090
• Publication Number:
  US 20110084389A1
• Time in Patent Office: 1,229 Days
• Field of Search: 438/108, 257/778, 257/E21.503
• US Class Current: 257/737
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/0558 being stacked
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05672 Vanadium [V] as principal constituent
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13083 Three-layer arrangements
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/73203 : Bump and layer connectors
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3192 : Multilayer coating
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49894 : Materials of the insulating layers or coatings
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

The present invention relates to a semiconductor device. The semiconductor device includes a substrate and a chip. The chip is electrically connected to the substrate. The chip includes a chip body, at least one chip pad, a first passivation, an under ball metal layer and at least one metal pillar structure. The chip pad is disposed adjacent to an active surface of the chip body. The first passivation is disposed adjacent to the active surface, and exposes part of the chip pad. The under ball metal layer is disposed adjacent to the chip pad. The metal pillar structure contacts the under ball metal layer to form a first contact surface having a first diameter. The metal pillar structure is electrically connected to a substrate pad of the substrate to form a second contact surface having a second diameter. The ratio of the first diameter to the second diameter is between 0.7 and 1.0. As a result, the first contact surface and the second contact surface have an equivalent bonding force, which prevents the metal pillar structure from cracking due to a shear stress. Thus, the structure strength of the semiconductor device is enhanced and the semiconductor device can pass the reliability test.

Claims

1. A semiconductor device, comprising:

a substrate, including;

a first surface;

at least one substrate pad, the substrate pad being disposed adjacent to the first surface; and

a solder mask disposed adjacent to the first surface and partially covering the substrate pad, the solder mask defining at least one solder mask opening so as to expose a part of the substrate pad;

a chip, disposed adjacent to the first surface of the substrate and electrically connected to the substrate, the chip including;

a chip body, including an active surface;

at least one chip pad, disposed adjacent to the active surface;

a first passivation, disposed adjacent to the active surface, and defining at least one first passivation opening so as to expose part of the chip pad; and

an under ball metal layer, disposed adjacent to the chip pad;

at least one metal pillar structure, wherein the metal pillar structure contacts the under ball metal layer to form a first contact surface having a first diameter, the metal pillar structure contacts the exposed part of the substrate pad to form a second contact surface having a second diameter, the first diameter is less than the second diameter, and the second diameter is substantially equal to a diameter of the solder mask opening; and

an underfill extending from the first passivation to the solder mask and circumscribing the at least one metal pillar structure.

2. The semiconductor device as claimed in claim 1, wherein the substrate further comprises a second surface and at least one solder ball, and the solder ball is disposed adjacent to the second surface.

3. The semiconductor device as claimed in claim 1, wherein a diameter of the first passivation opening is less than the second diameter of the exposed part of the substrate pad.

4. The semiconductor device as claimed in claim 1, wherein a diameter of the under ball metal layer substantially equals the first diameter.

5. The semiconductor device as claimed in claim 1, wherein the under ball metal layer is a multi-layered structure.

6. The semiconductor device as claimed in claim 1, wherein the metal pillar structure comprises a metal pillar and a solder, the metal pillar contacts the under ball metal layer to form the first contact surface, the solder is disposed adjacent to the metal pillar, and contacts the substrate pad of the substrate to form the second contact surface.

7. The semiconductor device as claimed in claim 6, wherein the external surface of the metal pillar is substantially aligned with the external surface of the under ball metal layer.

8. The semiconductor device as claimed in claim 6, wherein the material of the metal pillar is copper (Cu).

9. The semiconductor device as claimed in claim 6, wherein the metal pillar structure further comprises a barrier layer disposed between the metal pillar and the solder.

10. The semiconductor device as claimed in claim 9, wherein the material of the barrier layer is nickel (Ni).

11. A semiconductor device, comprising:

a substrate, including;

a first surface;

at least one substrate pad, the substrate pad being disposed adjacent to the first surface; and

a solder mask disposed adjacent to the first surface and partially covering the substrate pad, the solder mask defining at least one solder mask opening so as to expose a part of the substrate pad;

a chip, disposed adjacent to the first surface of the substrate and electrically connected to the substrate, the chip including;

a chip body, including an active surface;

at least one chip pad, disposed adjacent to the active surface;

a first passivation, disposed adjacent to the active surface, and defining at least one first passivation opening so as to expose part of the chip pad;

a second passivation disposed adjacent to the first passivation and having at least one second passivation opening so as to expose part of the chip pad; and

an under ball metal layer, disposed adjacent to the chip pad;

at least one metal pillar structure, wherein the metal pillar structure contacts the under ball metal layer to form a first contact surface having a first diameter, the metal pillar structure contacts the exposed part of the substrate pad to form a second contact surface having a second diameter, the first diameter is less than the second diameter, and the second diameter is substantially equal to a diameter of the solder mask opening; and

an underfill extending from the second passivation to the solder mask and circumscribing the at least one metal pillar structure.

12. The semiconductor device as claimed in claim 11, wherein the material of the second passivation is polyimide (PI).

13. The semiconductor device as claimed in claim 11, wherein the second passivation opening is smaller than the first passivation opening.

14. The semiconductor device as claimed in claim 11, wherein the second passivation opening is larger than the first passivation opening, and the second passivation opening further exposes part of the first passivation.

15. The semiconductor device as claimed in claim 11, further comprising a molding compound encapsulating part of the substrate and the chip.

16. The semiconductor device as claimed in claim 11, further comprising a molding compound, wherein the molding compound encapsulates part of the substrate, the chip and the underfill.

17. A semiconductor device, comprising:

a substrate, including;

a first surface;

at least one substrate pad, the substrate pad being disposed adjacent to the first surface; and

a solder mask disposed adjacent to the first surface and defining an exposed portion of the substrate pad smaller than the substrate pad;

a chip, disposed adjacent to the first surface of the substrate and electrically connected to the substrate, the chip including;

a chip body, including an active surface;

at least one chip pad, disposed adjacent to the active surface;

a first passivation, disposed adjacent to the active surface, and defining at least one first opening so as to expose part of the chip pad; and

an under ball metal layer, disposed adjacent to the chip pad; and

at least one metal pillar structure, wherein the metal pillar structure contacts the under ball metal layer to form a first contact surface having a first area, the metal pillar structure contacts the exposed portion of the substrate pad to form a second contact surface having a second area, the first area is smaller than the second area, and the second area is substantially equal to the exposed portion of the substrate pad.

18. The semiconductor device as claimed in claim 17, wherein the metal pillar structure comprises a metal pillar and a solder, the metal pillar contacts the under ball metal layer to form the first contact surface, the solder is disposed adjacent to the metal pillar, and contacts the substrate pad of the substrate to form the second contact surface.

19. The semiconductor device as claimed in claim 17, further comprising a second passivation disposed adjacent to the first passivation and having at least one second passivation opening so as to expose part of the chip pad, wherein the second passivation opening is smaller than the first passivation opening.

20. The semiconductor device as claimed in claim 17, further comprising a second passivation disposed adjacent to the first passivation and having at least one second passivation opening so as to expose part of the chip pad, wherein the second passivation opening is larger than the first passivation opening, and the second passivation opening further exposes part of the first passivation.