System for reducing noise in a chemical sensor array
First Claim
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1. A method comprising:
- receiving, at a first analog-to-digital converter, an output signal from a sensor array;
providing power, with a first switcher, to the sensor array and to the first analog-to-digital converter;
generating a plurality of clock signals that are synchronous with a primary clock signal; and
providing a first clock signal of the plurality to the first analog-to-digital converter and providing a second clock signal of the plurality to the first switcher, the first clock signal is asynchronous with the second clock signal.
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Abstract
A method including receiving an output signal from a sensor array, providing power to the sensor array and to the first analog-to-digital converter, generating a plurality of clock signals that are synchronous with a primary clock signal, providing a first clock signal of the plurality to the first analog-to-digital converter and providing a second clock signal of the plurality to the first switcher. The first clock signal is asynchronous with the second clock signal.
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Citations
12 Claims
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1. A method comprising:
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receiving, at a first analog-to-digital converter, an output signal from a sensor array; providing power, with a first switcher, to the sensor array and to the first analog-to-digital converter; generating a plurality of clock signals that are synchronous with a primary clock signal; and providing a first clock signal of the plurality to the first analog-to-digital converter and providing a second clock signal of the plurality to the first switcher, the first clock signal is asynchronous with the second clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method comprising:
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receiving, at a first analog-to-digital converter, an output signal from a sensor array; providing power, with a first switcher, to the sensor array and to the first analog-to-digital converter; generating a plurality of clock signals that are synchronous with a primary clock signal; providing a first clock signal of the plurality to the first analog-to-digital converter and providing a second clock signal of the plurality to the first switcher, the first clock signal is asynchronous with the second clock signal; and providing a power supply to provide power to a first switcher on a first substrate and providing power to a second switcher on a second substrate via the first switcher.
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Specification