System for reducing noise in a chemical sensor array

• US 8,552,771 B1
• Filed: 04/22/2013
• Issued: 10/08/2013
• Est. Priority Date: 05/29/2012
• Status: Active Grant

• Current Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Original Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Inventors: Rearick, Todd, Jordan, Jeremy
• Primary Examiner(s): ROJAS, DANIEL E
• Application Number:
  US13/867,959
• Time in Patent Office: 169 Days
• Field of Search: 327/141
• US Class Current: 327/141
• CPC Class Codes: G01N 27/4145 specially adapted for biomolecules, e.g. gate electrode with immobilised receptors
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 19/00346 Modifications for eliminating interference or parasitic voltages or currents

Abstract

A method including receiving an output signal from a sensor array, providing power to the sensor array and to the first analog-to-digital converter, generating a plurality of clock signals that are synchronous with a primary clock signal, providing a first clock signal of the plurality to the first analog-to-digital converter and providing a second clock signal of the plurality to the first switcher. The first clock signal is asynchronous with the second clock signal.

Claims

1. A method comprising:

receiving, at a first analog-to-digital converter, an output signal from a sensor array;

providing power, with a first switcher, to the sensor array and to the first analog-to-digital converter;

generating a plurality of clock signals that are synchronous with a primary clock signal; and

providing a first clock signal of the plurality to the first analog-to-digital converter and providing a second clock signal of the plurality to the first switcher, the first clock signal is asynchronous with the second clock signal.

2. The method of claim 1, further comprising:

providing an array of chemically-sensitive field effect transistors (chemFETs).

3. The method of claim 2, further comprising:

detecting a chemical reaction occurring proximate to the chemFETs.

4. The method of claim 1, further comprising:

receiving output signals from the sensor array at an output circuit.

5. The method of claim 4, further comprising:

providing the output signals to the first analog-to-digital converter.

6. The method of claim 1, further comprising:

providing a second switcher responsive to a third clock signal that is asynchronous with the first clock signal such that a power consumption on a power supply is staggered.

7. The method of claim 1, further comprising:

providing a second switcher responsive to a third clock signal having a rising edge that is concurrent with a falling edge of the first clock signal.

8. The method of claim 1, further comprising:

disposing the first and second switchers on a same substrate.

9. The method of claim 1, further comprising:

disposing the analog-to-digital converter and the sensor array on a same substrate.

10. The method of claim 1, further comprising:

disposing the analog-to-digital converter on a first substrate and disposing the sensor array on a second substrate.

11. The method of claim 1, further comprising:

providing a power supply to provide power to a first switcher on a first substrate and to provide power to a second switcher on a second substrate.

12. A method comprising:

receiving, at a first analog-to-digital converter, an output signal from a sensor array;

providing power, with a first switcher, to the sensor array and to the first analog-to-digital converter;

generating a plurality of clock signals that are synchronous with a primary clock signal;

providing a first clock signal of the plurality to the first analog-to-digital converter and providing a second clock signal of the plurality to the first switcher, the first clock signal is asynchronous with the second clock signal; and

providing a power supply to provide power to a first switcher on a first substrate and providing power to a second switcher on a second substrate via the first switcher.