System and method for a coreless transformer

• US 8,552,828 B1
• Filed: 09/07/2012
• Issued: 10/08/2013
• Est. Priority Date: 09/07/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Beer, Gottfried, Kilger, Thomas, Elrod, Urs, Brunner, Christiane
• Primary Examiner(s): Musleh, Mohamad
• Assistant Examiner(s): LIAN, MANG TIN BIK
• Application Number:
  US13/607,295
• Time in Patent Office: 396 Days
• Field of Search: 336/200, 336/223, 336/232, 336/192, 336/182
• US Class Current: 336/192
• CPC Class Codes: H01F 2027/2819 Planar transformers with printed windings, e.g. surrounded by two cores and to be mounted on printed circuit
• CPC Class Codes: H01F 27/2804 Printed windings
• CPC Class Codes: H01F 41/041 Printed circuit coils apparatus or processes for manufacturing printed circuits in general H05K3/00
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: Y10T 29/4902 Electromagnet, transformer or inductor
• CPC Class Codes: Y10T 29/49071 by winding or coiling

Abstract

In accordance with an embodiment, a transformer includes a first coil disposed in a first conductive layer on a first side of a first dielectric layer, and a second coil disposed in a second conductive layer on a second side of the first dielectric layer. Each coil has a first end disposed inside its respective coil and a second end disposed at an outer perimeter of its respective coil. A first crossover disposed in the second conductive layer is directly connected to the first end of the first coil and extends past the outer perimeter of the first coil. In addition, a second crossover disposed in the first conductive layer is directly connected to the first end of the second coil and extends past the outer perimeter of the second coil.

Claims

1. A transformer comprising:

a first dielectric layer;

a first coil disposed in a first conductive layer on a first side of the first dielectric layer, the first coil comprising a first end disposed inside the first coil, and a second end disposed at an outer perimeter of the first coil;

a second coil disposed in a second conductive layer on a second side of the first dielectric layer, the second side opposite the first side, the second coil comprising a first end disposed inside the second coil, and a second end disposed at an outer perimeter of the second coil;

a first crossover disposed in the second conductive layer, the first crossover directly connected to the first end of the first coil and extending past the outer perimeter of the first coil; and

a second crossover disposed in the first conductive layer, the second crossover directly connected to the first end of the second coil and extending past the outer perimeter of the second coil.

2. The transformer according to claim 1, wherein:

the first end of the second coil is disposed outside the outer perimeter of the first coil; and

the first end of the second coil is disposed outside the outer perimeter of the second coil.

3. The transformer according to claim 1, wherein:

a first lateral distance between the first crossover and a nearest portion of the second coil is not less than a first critical distance; and

a second lateral distance between the second crossover and a nearest portion of the first coil is not less than a second critical distance.

4. The transformer according to claim 3, wherein the first critical distance and the second critical distance are a same distance.

5. The transformer according to claim 3, wherein the first critical distance is between about 2 and about 5 times a width of the first dielectric layer.

6. The transformer according to claim 1, wherein the transformer is configured to withstand a potential difference of at least 2.5 kV between the first coil and the second coil.

7. The transformer according to claim 1, wherein the first coil and the second coil each comprise a spiral inductor.

8. The transformer according to claim 1, wherein the first coil and the second coil each comprise at least two turns.

9. The transformer according to claim 1, wherein the first conductive layer, the first dielectric layer and the second conductive layer are disposed on an integrated circuit.

10. The transformer according to claim 1, wherein the first conductive layer, the first dielectric layer and the second conductive layer comprise layers in a wafer level package.

11. The transformer according to claim 10, wherein the wafer level package includes only two conductive layers that form the first conductive layer and the second conductive layer and at least one non-conductive layer that forms the first dielectric layer.

12. The transformer according to claim 10, wherein the wafer level package comprises at least one integrated circuit disposed on the second conductive layer.

13. The transformer according to claim 10, wherein the wafer level package comprises:

a redistribution layer;

at least one integrated circuit disposed on the redistribution layer; and

an encapsulating layer disposed over the at least one integrated circuit, wherein the first conductive layer is disposed over the encapsulating layer.

14. The transformer according to claim 13, wherein the wafer level package further comprises through encapsulant vias coupling the redistribution layer with the first conductive layer and the second conductive layer.

15. The transformer according to claim 10, wherein the wafer level package comprises

at least one integrated circuit disposed over the first conductive layer, wherein:

the first dielectric layer is formed as an encapsulating layer disposed over the at least one integrated circuit; and

the second conductive layer is formed over the encapsulating layer.

16. The transformer of claim 1, wherein:

the transformer is coupled to a transceiver disposed on a same integrated circuit as the transformer; and

a majority of a surface area of the first coil in the first conductive layer on the first side of the dielectric layer is disposed directly opposite from a majority of a surface area of the second coil disposed on the second side of the first dielectric layer.

17. The transformer of claim 1, wherein:

the transformer is coupled to a transceiver that is disposed on a same integrated circuit as the transformer; and

the first coil is laterally offset from the second coil, and

a majority of a surface area of the first coil in the first conductive layer on the first side of the dielectric layer is not disposed directly opposite from a majority of a surface area of the second coil disposed on the second side of the first dielectric layer.

18. The transformer of claim 1, wherein:

the transformer is coupled to a transceiver that is disposed on an integrated circuit that separate from the transformer; and

a majority of a surface area of the first coil in the first conductive layer on the first side of the dielectric layer is disposed directly opposite from a majority of a surface area of the second coil disposed on the second side of the first dielectric layer.

19. The transformer of claim 1, wherein:

the transformer is coupled to a transceiver that is disposed on an integrated circuit that separate from the transformer; and

the first coil is laterally offset from the second coil, and

a majority of a surface area of the first coil in the first conductive layer on the first side of the dielectric layer is not disposed directly opposite from a majority of a surface area of the second coil disposed on the second side of the first dielectric layer.

20. A wafer level package comprising:

a first dielectric layer;

a first conductive layer disposed on a first side of the first dielectric layer;

a second conductive layer disposed on a second side of the first dielectric layer, the second side opposite the first side;

a first coil disposed in the first conductive layer, the first coil comprising a first end disposed inside the first coil, and a second end disposed at an outer perimeter of the first coil;

a second coil disposed in the second conductive layer, the second coil comprising a first end disposed inside the second coil, and a second end disposed at an outer perimeter of the second coil;

a first crossover disposed in the second conductive layer, the first crossover directly connected to the first end of the first coil and extending past the outer perimeter of the first coil; and

a second crossover disposed in the first conductive layer, the second crossover directly connected to the first end of the second coil and extending past the outer perimeter of the second coil.

21. The wafer level package according to claim 20, wherein the first coil and the second coil form a transformer.

22. The wafer level package according to claim 21, wherein the transformer is an isolation transformer configured to withstand a potential difference of at least 2.5 kV between the first coil and the second coil.

23. The wafer level package according to claim 20, wherein:

the first end of the second coil is disposed outside the outer perimeter of the first coil; and

the first end of the second coil is disposed outside the outer perimeter of the second coil.

24. The wafer level package according to claim 20, wherein:

a first lateral distance between the first crossover and a nearest portion of the second coil is not less than a first critical distance; and

a second lateral distance between the second crossover and a nearest portion of the first coil is not less than a second critical distance.

25. The wafer level package according to claim 20, further comprising an integrated circuit coupled to the first coil.

26. The wafer level package according to claim 20, wherein, wherein the wafer level package comprises redistribution layers having only two conductive layers and at least one non-conductive layer, wherein the only two conductive layers comprise the first conductive layer and the second conductive layer.

27. The wafer level package according to claim 20, further comprising:

at least one integrated circuit disposed over the second conductive layer; and

an encapsulating material disposed over the at least one integrated circuit.

28. The wafer level package according to claim 20, wherein the first coil and the second coil are disposed in a fan out area of the wafer level package.

29. The wafer level package according to claim 20, further comprising at least one integrated circuit disposed over the first conductive layer, wherein the first dielectric layer comprises an encapsulating material disposed over the at least one integrated circuit.

30. The wafer level package according to claim 29, further comprising through encapsulant vias coupling the first conductive layer and the second conductive layer at the first crossover and at the second crossover.

31. The wafer level package according to claim 20, further comprising:

at least one integrated circuit disposed over a redistribution layer; and

an encapsulating material disposed over the at least one integrated circuit, wherein the first conductive layer, first dielectric layer, and second conductive layer are disposed over the encapsulating material.

32. A method of forming a transformer, the method comprising:

forming a second coil in a second conductive layer;

forming a first crossover in the second conductive layer;

forming a first dielectric layer over the second conductive layer;

forming a first coil in a first conductive layer disposed over the first dielectric layer; and

forming a second crossover in the first conductive layer, wherein;

the first coil comprises a first end disposed inside the first coil, and a second end disposed at an outer perimeter of the first coil,

the second coil comprises a first end disposed inside the second coil, and a second end disposed at an outer perimeter of the second coil,

the first crossover is coupled to the first end of the first coil and extends past the outer perimeter of the first coil, and

the second crossover is coupled to the first end of the second coil and extends past the outer perimeter of the second coil.

33. The method according to claim 32, wherein forming the second conductive layer comprises forming the second conductive layer over a semiconductor substrate.

34. The method according to claim 32, further comprising forming a wafer level package comprising only two conductive layers and at least one non-conductive layer that include the first conductive layer and the second conductive layer, and the first dielectric layer.