Semiconductor memory device and driving method thereof
First Claim
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1. A semiconductor memory device comprising:
- one or more main bit lines;
one or more power supply lines;
four or more word lines; and
two or more cells,wherein each of the cells includes a sub bit line, a selection transistor, a reading transistor, and two or more memory cells,wherein a drain of the selection transistor and a drain of the reading transistor are connected to one of the main bit lines,wherein a gate of the reading transistor is connected to the sub bit line,wherein a source of the reading transistor is connected to one of the power supply lines,wherein each of the memory cells includes a transistor and a capacitor,wherein the capacitance of the capacitor is 1 fF or less, andwherein a gate of the transistor of one of the memory cells is connected to one of the word lines.
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Abstract
In a conventional DRAM, errors in reading data are likely to occur when the capacitance of a capacitor is reduced. A plurality of cells is connected to one main bit line Each cell includes a sub bit line and 2 to 32 memory cells. Further, each cell includes a selection transistor and a reading transistor, and a sub bit line is connected to a gate of the reading transistor. Since the parasitic capacitance of the sub bit line is sufficiently small, data of electric charge of a capacitor of each memory cell can be amplified without an error in the reading transistor and output to the main bit line.
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Citations
16 Claims
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1. A semiconductor memory device comprising:
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one or more main bit lines; one or more power supply lines; four or more word lines; and two or more cells, wherein each of the cells includes a sub bit line, a selection transistor, a reading transistor, and two or more memory cells, wherein a drain of the selection transistor and a drain of the reading transistor are connected to one of the main bit lines, wherein a gate of the reading transistor is connected to the sub bit line, wherein a source of the reading transistor is connected to one of the power supply lines, wherein each of the memory cells includes a transistor and a capacitor, wherein the capacitance of the capacitor is 1 fF or less, and wherein a gate of the transistor of one of the memory cells is connected to one of the word lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A semiconductor memory device comprising:
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a first main bit line and a second main bit line; one or more power supply lines; four or more word lines; a first cell and a second cell, wherein the first cell includes a first sub bit line, a first selection transistor, a first reading transistor, and two or more memory cells, wherein the second cell includes a second sub bit line, a second selection transistor, a second reading transistor, and two or more memory cells, wherein a drain of the first selection transistor and a drain of the first reading transistor are connected to the first main bit line, wherein a source of the first selection transistor and a gate of the second reading transistor are connected to the first sub bit line, wherein a source of the first reading transistor is connected to one of the power supply lines, wherein each of the memory cells includes a transistor and a capacitor, wherein the capacitance of the capacitor is 1 fF or less, and wherein a gate of the transistor of one of the memory cells is connected to one of the word lines. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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Specification