Non-volatile memory with dynamic multi-mode operation

• US 8,553,457 B2
• Filed: 02/01/2013
• Issued: 10/08/2013
• Est. Priority Date: 02/16/2007
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Kim, Jin-Ki
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US13/757,250
• Publication Number:
  US 20130141973A1
• Time in Patent Office: 249 Days
• Field of Search: 365/185.03, 365/185.01, 365/185.11, 365/185.12, 365/185.33, 365/168
• US Class Current: 365/185.03
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7204 Capacity control, e.g. partitioning, end-of-life degradation
• CPC Class Codes: G06F 2212/7206 Reconfiguration of flash memory system
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 2211/5646 Multilevel memory with flag bits, e.g. for showing that a "first page" of a word line is programmed but not a "second page"

Abstract

A method and system for extending the life span of a flash memory device. The flash memory device is dynamically configurable to store data in the single bit per cell (SBC) storage mode or the multiple bit per cell (MBC) mode. In the MBC storage mode, the cell can have one of multiple possible states, where each state is defined by respective threshold voltage ranges. In the SBC mode, the cell can have states with threshold voltages corresponding to states of the MBC storage mode which are non-adjacent to each other to improve reliability characteristics of the cell.

Claims

1. A method carried out in a memory device having a plurality of non-volatile memory cells, and each non-volatile memory cell of the non-volatile memory cells having multiple possible states being defined by respective threshold voltage ranges including a first voltage range, a second voltage range, a third voltage range and a fourth voltage range, the second voltage range being adjacent to a lowest voltage range which is the first voltage range, the third voltage range being in-between the second and fourth voltage ranges, and the method comprising:

when operating the non-volatile memory cell in a Multiple Bit per Cell (MBC) storage mode, storing more than one bit of data by;

carrying out lower page programming, the lower page programming being a first stage of programming; and

carrying out upper page programming, the upper page programming being a second stage of programming; and

when operating the non-volatile memory cell in a Single Bit per Cell (SBC) storage mode, storing a single bit of data by;

carrying out single stage programming; and

using only the first voltage range and the fourth voltage range to store the single bit of data.

2. The method as claimed in claim 1 wherein the non-volatile memory cell is a NAND flash memory cell.

3. The method as claimed in claim 1 wherein the first voltage range is a negative voltage range.

4. The method as claimed in claim 1 wherein the first voltage range corresponds to an erased state.

5. The method as claimed in claim 1 wherein the fourth voltage range is a positive voltage range.

6. A memory device comprising:

a plurality of non-volatile memory cells, each non-volatile memory cell of the non-volatile memory cells having multiple possible states being defined by respective threshold voltage ranges including a first voltage range, a second voltage range, a third voltage range and a fourth voltage range, the second voltage range being adjacent to a lowest voltage range which is the first voltage range, the third voltage range being in-between the second and fourth voltage ranges; and

when operated in a Multiple Bit per Cell (MBC) storage mode, the non-volatile memory cell to store more than one bit of data by;

the memory device first carrying out lower page programming, the lower page programming being a first stage of programming; and

the memory device then carrying out upper page programming, the upper page programming being a second stage of programming; and

when operated in a Single Bit per Cell (SBC) storage mode, the non-volatile memory cell to store a single bit of data by;

the memory device carrying out single stage programming, and only the first voltage range and the fourth voltage range being used to store the single bit of data.

7. The memory device as claimed in claim 6 wherein the non-volatile memory cell is a NAND flash memory cell.

8. The memory device as claimed in claim 6 wherein the first voltage range is a negative voltage range.

9. The memory device as claimed in claim 6 wherein the first voltage range corresponds to an erased state.

10. The memory device as claimed in claim 6 wherein the fourth voltage range is a positive voltage range.

11. A method carried out in a memory device having a plurality of non-volatile memory cells, and each non-volatile memory cell of the non-volatile memory cells having multiple possible states being defined by respective threshold voltage ranges including a first voltage range, a second voltage range, a third voltage range and a fourth voltage range, the second voltage range being adjacent to a lowest voltage range which is the first voltage range, the third voltage range being in-between the second and fourth voltage ranges, and the method comprising:

erasing the non-volatile memory cell; and

after the erasing, carrying out programming to store, in the non-volatile memory cell, and using the first and third voltage ranges but not the second and fourth voltage ranges, an amount of data one bit less than a cell capacity of the non-volatile memory cell.

12. The method as claimed in claim 11 wherein the non-volatile memory cell is a NAND flash memory cell.

13. The method as claimed in claim 11 wherein the first voltage range is a negative voltage range.

14. The method as claimed in claim 11 wherein the non-volatile memory cell has, at least when operated in a Multiple Bit per Cell (MBC) storage mode, a configured capacity for storing two bits of data.

15. The method as claimed in claim 11 wherein the non-volatile memory cell has, at least when operated in an MBC storage mode, a configured capacity for storing more than two bits of data.

16. A memory device comprising:

a plurality of non-volatile memory cells, each non-volatile memory cell of the non-volatile memory cells having multiple possible states being defined by respective threshold voltage ranges including a first voltage range, a second voltage range, a third voltage range and a fourth voltage range, the second voltage range being adjacent to a lowest voltage range which is the first voltage range, the third voltage range being in-between the second and fourth voltage ranges; and

the memory device being configured to;

erase the non-volatile memory cell; and

after erasing the non-volatile memory cell, carry out programming to store, in the non-volatile memory cell, and using the first and third voltage ranges but not the second and fourth voltage ranges, an amount of data one bit less than a cell capacity of the non-volatile memory cell.

17. The memory device as claimed in claim 16 wherein the non-volatile memory cell is a NAND flash memory cell.

18. The memory device as claimed in claim 16 wherein the first voltage range is a negative voltage range.

19. The memory device as claimed in claim 16 wherein the non-volatile memory cell has, at least when operated in a Multiple Bit per Cell (MBC) storage mode, a configured capacity for storing two bits of data.

20. The memory device as claimed in claim 16 wherein the non-volatile memory cell has, at least when operated in an MBC storage mode, a configured capacity for storing more than two bits of data.