Non-volatile memory device, erasing method thereof, and memory system including the same

• US 8,553,466 B2
• Filed: 02/09/2011
• Issued: 10/08/2013
• Est. Priority Date: 03/04/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Han, Jinman, Kim, Doogon
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US13/023,934
• Publication Number:
  US 20110216603A1
• Time in Patent Office: 972 Days
• Field of Search: 365/185.29, 365/185.27, 365/185.23, 365/185.18, 365/185.24
• US Class Current: 365/185.29
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

Provided is an erasing method of a nonvolatile memory device. The erasing method applies a word line erase voltage to a plurality of word lines connected to the memory cells respectively, applies a specific voltage to a ground selection line connected to the ground selection transistor, applies an erase voltage to a substrate in which the memory string formed during the step applying the specific voltage to the ground selection line, and floats the ground selection line in response to a voltage change of the substrate.

Claims

1. An erasing method of a nonvolatile memory device having a memory string including a plurality of memory cells, a string selection transistor, and a ground selection transistor, the erasing method comprising:

applying a word line erase voltage to a plurality of word lines connected to the memory cells respectively;

applying a specific voltage to a ground selection line connected to the ground selection transistor;

applying an erase voltage to a substrate in which the memory string formed during the step applying the specific voltage to the ground selection line; and

floating the ground selection line in response to a voltage change of the substrate.

2. The erasing method of claim 1, wherein the applying of a specific voltage comprises applying a ground voltage to the ground selection line.

3. The erasing method of claim 1, wherein the floating of the ground selection line is performed when the voltage level of the substrate reaches a target voltage level.

4. The erasing method of claim 1, wherein the memory cells are stacked in a direction vertical to the substrate.

5. A nonvolatile memory device comprising:

a memory cell array comprising a plurality of memory cell strings which are provided onto a substrate;

a reading and writing circuit connected to the memory cell strings through a plurality of bit lines, and configured to drive the bit lines;

an address decoder connected to the memory cell strings through a plurality of word lines, a string selection line and a ground selection line, and configured to drive the word lines and the selection lines; and

a substrate monitor circuit monitoring a voltage level of the substrate wherein the address decoder drives the ground selection line according to a monitored result in an erasing operation.

6. The nonvolatile memory device of claim 5, wherein when an erasing voltage for the erase operation is started to be applied to the substrate, the address decoder is configured to drive the ground selection line to a ground voltage.

7. The nonvolatile memory device of claim 6, wherein during the erasing operation, the address decoder is configured to float the ground selection line when a voltage level of the substrate reaches a target voltage level.

8. The nonvolatile memory device of claim 5, wherein the substrate monitor circuit comprises:

first and second trimmers connected between a ground node and a substrate node to which a voltage of the substrate is provided; and

a comparator configured to compare a target voltage and a voltage of a node between the first and second trimmers to output the monitored result.

9. An erasing method of nonvolatile memory device, the method comprising:

providing the nonvolatile memory device including a memory string perpendicular to a substrate of a first conductivity, the memory string including a string select transistor, a plurality of memory cells and a ground select transistor using a pillar active body of the first conductivity contacting the substrate;

applying a word line erase voltage to a plurality of word lines connected to the plurality of memory cells;

applying a voltage to a ground selection line connected to the ground select transistor;

applying an erase voltage to the substrate; and

floating the ground selection line in response to a voltage shift of the substrate.

10. A nonvolatile memory device, comprising:

a substrate;

a memory string including a string select transistor, a plurality of memory cells and a ground select transistor using a pillar active body of a first conductivity contacting the substrate;

an address decoder configured to apply a word line erase voltage to a plurality of word lines connected to the plurality of memory cells and apply a voltage to a ground selection line connected to the ground select transistor;

a substrate bias circuit configured to apply an erase voltage to the substrate; and

a substrate monitor circuit configured to sense a voltage shift of the substrate, wherein the address decoder floats the ground selection line in response to the voltage shift of the substrate.

11. An erasing method of a nonvolatile memory device including a substrate and a plurality of memory blocks, each including a plurality of memory strings in a two-dimensional array, each including a string selection transistor, a plurality of memory cells, and a ground selection transistor, the plurality of memory strings arranged in rows and columns, wherein columns of the plurality of memory strings are each connected to a corresponding bit line by the corresponding string selection transistor and rows of the plurality of memory strings are each connected to a corresponding string select line by the corresponding string selection transistor, the method comprising;

selecting one of the plurality of memory blocks for erasing;

applying a word line erase voltage to a plurality of word lines connected to the plurality of memory cells of the selected memory block;

applying a voltage to a ground selection line connected to the ground select transistor of the selected memory block and not to at least one unselected memory blocks;

applying an erase voltage to the substrate; and

floating the ground selection line of the selected memory block in response to a voltage shift of the substrate.

12. The erasing method of claim 11, wherein the ground selection lines connected to the ground select transistors of the at least one unselected memory blocks are allowed to float.

13. The method of claim 11, wherein the voltage applied to the ground selection line connected to the ground select transistor of the selected memory block is a ground voltage.

14. The method of claim 11, wherein the voltage applied to the ground selection line connected to the ground select transistor of the selected memory block is allowed to float after the erase voltage reaches a threshold voltage.

15. The method of claim 11, further comprising:

monitoring a voltage of the substrate and when the voltage of the substrate reaches a threshold voltage, ceasing to apply the voltage to the ground selection line connected to the ground select transistor of the selected memory block.

16. The method of claim 11, further comprising:

floating the string selection lines connected to the string selection transistors for each of the plurality of memory blocks.

17. A nonvolatile memory device, comprising:

a substrate;

a plurality of memory blocks, each including a plurality of memory strings in a two-dimensional array, each string including a string selection transistor, a plurality of memory cells, and a ground selection transistor, the plurality of memory strings arranged in rows and columns, wherein columns of the plurality of memory strings are each connected to a corresponding bit line by the corresponding string selection transistor and rows of the plurality of memory strings are each connected to a corresponding string select line by the corresponding string selection transistor;

an address decoder configured to select one of the plurality of memory blocks for erasing, apply a word line erase voltage to a plurality of word lines connected to the plurality of memory cells of the selected memory block, apply a voltage to a ground selection line connected to the ground select transistor of the selected memory block and not to the unselected memory blocks;

a substrate bias circuit configured to apply an erase voltage to the substrate; and

a substrate monitor circuit configured to sense a voltage shift of the substrate, wherein the address decoder float the ground selection line in response to the voltage shift of the substrate.

18. The nonvolatile memory device of claim 17, wherein the address decoder allows the ground selection lines connected to the ground select transistors of the unselected memory blocks to float.

19. The nonvolatile memory device of claim 17, wherein the address decoder applies a ground voltage to the ground selection line connected to the ground select transistor of the selected memory block.

20. The nonvolatile memory device of claim 17, wherein the address decoder allows the voltage of the ground selection line connected to the ground select transistor of the selected memory block to float after the erase voltage reaches a threshold voltage.

21. The nonvolatile memory device of claim 17, wherein

the substrate monitor circuit is adapted to monitor a voltage of the substrate and when the voltage of the substrate reaches a threshold voltage generate a ground enable signal, the address decoder ceasing to apply the voltage to the ground selection line connected to the ground select transistor of the selected memory block, in response to the ground enable signal and then floating the ground selection line.

22. The nonvolatile memory device of claim 21, the substrate monitor circuit further including,

first and second trimmers connected between a ground node and a substrate node to which the erase voltage of the substrate is provided;

and

a comparator configured to compare a target voltage and a voltage of a node between the first and second trimmers and output a comparison result to the address decoder.

23. The nonvolatile memory device of claim 22, wherein if the comparison result indicates the voltage of the substrate has reached the threshold voltage, the address decoder stops applying the voltage to a ground selection line connected to the ground select transistor of the selected memory block.

24. The nonvolatile memory device of claim 17, the address decoder further floating the string selection line for each of the plurality of memory blocks.

25. The nonvolatile memory device of claim 21, the address decoder further including

at least two block word line drivers, each configured to generate a block selection signal,

a string selection line driver, configured to drive a string selection line of the plurality of memory blocks in response to the block selection signal,

a word line driver, configured to drive word lines of the plurality of memory blocks in response to the block selection signal,

a ground selection line driver, configured to drive a ground select line of one of the plurality of memory blocks and to receive the ground enable signal from the substrate monitor circuit and

a pass circuit, configured to transfer voltages driven by the string selection line driver, the word line driver, and the ground selection line driver to the corresponding lines of the selected one of the plurality of memory blocks in response to the block selection signal.

26. The nonvolatile memory device of claim 25, wherein the pass circuit includes a plurality of transistors, one to control each of the word lines, each of the string select lines, and each of the ground selection lines.

27. A nonvolatile memory device comprising:

a memory cell array comprising a plurality of memory cell strings which are provided onto a substrate;

a reading and writing circuit connected to the memory cell strings through a plurality of bit lines, and configured to drive the bit lines; and

an address decoder connected to the memory cell strings through a plurality of word lines, a string selection line and a ground selection line, and configured to drive the word lines and the selection lines;

wherein the address decoder drives the ground selection line in an erasing operation by waiting a delay time after applying a voltage to the substrate.

28. The nonvolatile memory device of claim 27, wherein when an erasing voltage for the erase operation is started to be applied to the substrate, the address decoder is configured to drive the ground selection line to a ground voltage.

29. The nonvolatile memory device of claim 27, wherein during the erasing operation, the address decoder is configured to float the ground selection line when a voltage level of the substrate reaches a target voltage level.

30. A nonvolatile memory device, comprising:

a substrate;

a memory string including a string select transistor, a plurality of memory cells and a ground select transistor using a pillar active body of a first conductivity contacting the substrate;

an address decoder configured to apply a word line erase voltage to a plurality of word lines connected to the plurality of memory cells and apply a voltage to a ground selection line connected to the ground select transistor;

a substrate bias circuit configured to apply an erase voltage to the substrate; and

wherein the address decoder waits a delay time and then floats the ground selection line in response to the voltage shift of the substrate.

31. A nonvolatile memory device, comprising:

a substrate;

a plurality of memory blocks, each including a plurality of memory strings in a two-dimensional array, each string including a string selection transistor, a plurality of memory cells, and a ground selection transistor, the plurality of memory strings arranged in rows and columns, wherein columns of the plurality of memory strings are each connected to a corresponding bit line by the corresponding string selection transistor and rows of the plurality of memory strings are each connected to a corresponding string select line by the corresponding string selection transistor;

an address decoder configured to select one of the plurality of memory blocks for erasing, apply a word line erase voltage to a plurality of word lines connected to the plurality of memory cells of the selected memory block, apply a voltage to a ground selection line connected to the ground select transistor of the selected memory block and not to the unselected memory blocks; and

a substrate bias circuit configured to apply an erase voltage to the substrate;

wherein the address decoder waits a delay time and then floats the ground selection line in response to the voltage shift of the substrate.

32. The nonvolatile memory device of claim 31, wherein the address decoder allows the ground selection lines connected to the ground select transistors of the unselected memory blocks to float.

33. The nonvolatile memory device of claim 31, wherein the address decoder applies a ground voltage to the ground selection line connected to the ground select transistor of the selected memory block.

34. The nonvolatile memory device of claim 31, wherein the address decoder allows the voltage of the ground selection line connected to the ground select transistor of the selected memory block to float after the erase voltage reaches a threshold voltage.

35. The nonvolatile memory device of claim 31, the address decoder further floating the string selection line for each of the plurality of memory blocks.

36. The nonvolatile memory device of claim 31, the address decoder further including

at least two block word line drivers, each configured to generate a block selection signal,

a string selection line driver, configured to drive a string selection line of the plurality of memory blocks in response to the block selection signal,

a word line driver, configured to drive word lines of the plurality of memory blocks in response to the block selection signal,

a ground selection line driver, configured to drive a ground select line of one of the plurality of memory blocks and to receive a time delay signal and

a pass circuit, configured to transfer voltages driven by the string selection line driver, the word line driver, and the ground selection line driver to the corresponding lines of the selected one of the plurality of memory blocks in response to the block selection signal.

37. The nonvolatile memory device of claim 36, wherein the pass circuit includes a plurality of transistors, one to control each of the word lines, each of the string select lines, and each of the ground selection lines.