Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules
First Claim
1. A method of accessing and processing data in memory comprising a plurality of electrically isolated sectors, each sector comprising at least one memory device, the method comprising:
- receiving at two or more memory devices of different sectors respective control and address signals;
processing the respective control and address signals; and
simultaneously accessing the two or more memory devices of different sectors based on the respective control and address signals.
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Accused Products
Abstract
A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time. In an alternate embodiment, the printed circuit board includes a driver sector electrically isolated from the other sectors and having a multi-layer structure, the driver being attached to the driver sector.
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Citations
22 Claims
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1. A method of accessing and processing data in memory comprising a plurality of electrically isolated sectors, each sector comprising at least one memory device, the method comprising:
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receiving at two or more memory devices of different sectors respective control and address signals; processing the respective control and address signals; and simultaneously accessing the two or more memory devices of different sectors based on the respective control and address signals. - View Dependent Claims (2, 3, 4, 5)
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6. A method of accessing and processing data in a memory comprising a plurality of memory devices organized into a plurality of memory ranks, each memory rank comprising a plurality of electrically isolated memory devices, the method comprising:
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receiving at two or more electrically isolated memory devices of one or more memory ranks respective control and address signals; processing the respective control and address signals; and simultaneously accessing the two or more electrically isolated memory devices of one or more memory ranks based on the respective control and address signals. - View Dependent Claims (7, 8, 9, 10, 11, 12)
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13. A method of accessing and processing data in a memory comprising a plurality of memory devices divided into a plurality of memory ranks, each memory rank comprising a plurality of electrically-isolated memory devices, the method comprising:
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receiving at two or more memory ranks respective control and address signals; processing the respective control and address signals; and simultaneously accessing the two or more memory ranks based on the respective control and address signals. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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20. A method of accessing and processing data in a memory comprising a plurality of memory devices segmented into a plurality of electrically-isolated memory sectors, each memory sector comprising a plurality of memory devices, the method comprising:
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receiving at two or more memory sectors respective control and address signals; processing the respective control and address signals; and simultaneously accessing the two or more memory sectors based on the respective control and address signals. - View Dependent Claims (21, 22)
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Specification