Frequency generation using a single reference clock and a primitive ratio of integers

• US 8,554,815 B1
• Filed: 11/18/2009
• Issued: 10/08/2013
• Est. Priority Date: 11/09/2006
• Status: Active Grant

• Current Assignee: MACOM Connectivity Solutions, LLC (MACOM Technology Solutions Holdings, Inc.)
• Original Assignee: Applied Micro Circuits Corporation (MACOM Technology Solutions Holdings, Inc.)
• Inventors: Do, Viet Linh, Pang, Simon
• Primary Examiner(s): Tsai, Henry
• Assistant Examiner(s): Phan, Dean
• Application Number:
  US12/621,361
• Time in Patent Office: 1,420 Days
• Field of Search: 708/271
• US Class Current: 708/271
• CPC Class Codes: E02F 3/3604 Devices to connect tools to arms, booms or the like
• CPC Class Codes: E02F 3/3609 of the quick acting type, e.g. controlled from the operator seat quick-acting couplers to connect booms or arms to tractors E02F3/627; quick-acting couplers for machines mounted on tractor A01B59/06; couplings of the quick-acting type per se F16L37/00
• CPC Class Codes: E02F 9/006 Pivot joint assemblies in general F16C11/04

Abstract

A system and method are provided for synthesizing signal frequencies using a single reference clock and a primitive ratio of integers. The method accepts a plurality (k) of reference frequency values (f_rⁱ), where 1≦i≦k, associated with a corresponding plurality of synthesized frequency values (f_oⁱ). For each synthesized frequency value, a raw ratio of integers Np_rawⁱ and Dp_rawⁱ is calculated, such that:

$f_o^i=\frac{{\mathrm{Np}}_{\mathrm{raw}}^i}{{\mathrm{Dp}}_{\mathrm{raw}}^i}\times f_r^i.$

A greatest common divisor (GCD) of Np_rawⁱ and Dp_rawⁱ and a primitive ratio of integers

$\frac{{\mathrm{Np}}^i}{{\mathrm{Dp}}^i}$
is found for each raw ratio of integers, such that:

$N_p^i=\frac{{\mathrm{Np}}_{\mathrm{raw}}^i}{\mathrm{GCD}\left({\mathrm{Np}}_{\mathrm{raw}}^i,{\mathrm{Dp}}_{\mathrm{raw}}^i\right)};\mathrm{and},D_p^i=\frac{{\mathrm{Dp}}_{\mathrm{raw}}^i}{\mathrm{GCD}\left({\mathrm{Np}}_{\mathrm{raw}}^i,{\mathrm{Dp}}_{\mathrm{raw}}^i\right)}.$

Using the common clock frequency value (f_cr), each primitive ratio of integers, each reference frequency value, and each GCD, a final ratio of integers N_crⁱ and D_crⁱ,

$C·\left(\frac{N_{\mathrm{cr}}^i}{D_{\mathrm{cr}}^i}\right),$
is calculated for each synthesized frequency value, where C is an integer value.

Claims

1. In a frequency synthesis device, a method for synthesizing signal frequencies using a single reference clock and a primitive ratio of integers, the method comprising:

accessing a plurality (k) of reference clock frequency values (f_rⁱ), where 1≦

i≦

k, and also accessing a plurality of synthesized clock frequency values (f_oⁱ);

for each synthesized clock frequency value, calculating a raw ratio of integers Np_rawⁱ and Dp_rawⁱ, such that;

2. The method of claim 1 further comprising:

receiving a command to generate synthesized clock frequencies f_oⁱ;

accessing the memory to recover the final ratio of integers N_crⁱ and D_crⁱ,

3. The method of claim 1 wherein the calculation includes finding:

4. The method of claim 1 wherein the calculation includes finding:

5. The method of claim 2 wherein supplying the final ratio to the flexible accumulator module includes reducing the ratio

6. The method of claim 5 wherein reducing the ratio

7. The method of claim 5 wherein supplying

8. The method of claim 1 wherein calculating the final ratio of integers N_crⁱ and D_crⁱ,

9. In a frequency synthesis device, a system for synthesizing signal frequencies using a single reference clock and a primitive ratio of integers, the system comprising:

a calculator configured to accept a plurality (k) of reference clock frequency values (f_rⁱ), where 1≦

i≦

k, and to accept a plurality of synthesized clock frequency values (f_oⁱ), the calculator calculating a raw ratio of integers Np_rawⁱ and Dp_rawⁱ for each synthesized clock frequency value, such that;

10. The system of claim 9 wherein the memory has an input to accept a command to generate synthesized clock frequencies f_oⁱ;

the system further comprising;

a flexible accumulator having an interface operable for accessing the table in memory, in response to the command to generate the synthesized clock frequencies f_oⁱ, to recover the final ratio of integers

11. The system of claim 9 wherein the calculation includes finding:

12. The system of claim 9 wherein the calculation includes finding:

13. The system of claim 10 wherein the CRR module reduces the ratio C·

14. The system of claim 13 wherein the flexible accumulator module includes a plurality of series-connected flexible accumulators, where each flexible accumulator generates a binary sequence, and a plurality of binary sequences are used to generate the k-bit quotient.

15. The system of claim 13 wherein the flexible accumulator module accesses

16. The system of claim 9 wherein the CRR module calculates