Method and system for reducing packet latency in networks with both low latency and high bandwidths requirements

• US 8,554,943 B1
• Filed: 03/31/2006
• Issued: 10/08/2013
• Est. Priority Date: 03/31/2006
• Status: Active Grant

• Current Assignee: Emc IP Holding Company LLC (Dell Technologies Inc.)
• Original Assignee: EMC Corporation (Dell Technologies Inc.)
• Inventors: Walton, John K., Chilton, Kendell
• Primary Examiner(s): Lim, Krisna
• Assistant Examiner(s): DESAI, MARGISHI V
• Application Number:
  US11/278,157
• Time in Patent Office: 2,748 Days
• Field of Search: 370/503, 710/113, 709/232
• US Class Current: 709/232
• CPC Class Codes: H04L 47/245 using preemption
• CPC Class Codes: H04L 47/56 implementing delay-aware scheduling
• CPC Class Codes: H04L 47/6215 Individual queue per QOS, rate or priority

Abstract

A method and structure for detecting whether the packets received by the switch are low latency packets or high bandwidth packets and routing detected low latency packets to a first one of a pair of switching structures and for high bandwidth packets to a second one of the pair of switching structures. The switch includes an output section for detecting whether a low latency packet is being received during transmission of a high bandwidth packet and, under such detected condition interrupting the transmission of the high bandwidth packet, transmitting the low latency packet, and then transmitting a remaining portion of the high bandwidth packet. The switch inserts delimiters at the start of transmission of the low latency packet and an end of transmission of the low latency packet. The transmission of the low latency packet commences immediately upon detection of such low latency packet.

Claims

1. A switch, comprising:

(A) a low latency packet processor for processing low latency packets;

(B) a high bandwidth packet processor for processing high bandwidth packets; and

(C) a plurality of input/output sections, each one of the input/output sections comprising;

(i) an input section, comprising;

(a) a decode logic for receiving at a common port both low latency packets and high bandwidth packets; and

(b) wherein the decode logic detects whether each one of the received packets at the common port is a low latency packet or a high bandwidth packet and wherein the decode logic routes the received packets to either the low latency processor or to the high bandwidth processor selectively in accordance with whether the received packet is detected as a low latency packet or a high bandwidth packet; and

(ii) an output section having a pair of inputs, one of the pair of inputs being coupled to an output of the low latency packet processor and the other one of the pair of inputs being coupled to an output of the high bandwidth packet processor; and

(iii) wherein the output section;

(a) interrupts transmission the high bandwidth packets processed by the high bandwidth processor for transmission of the low latency packets processed by the low latency processor;

(b) inserts a start of low latency packet delimiter;

(c) transmits the low latency packet;

(d) inserts an end of low latency packet delimiter;

(e) and then continues the interrupted transmission of the high bandwidth packet after transmission of the low latency packet to provide at a common output of the output section both the transmitted high bandwidth packets and the transmitted low latency packets.