PCI express enhancements and extensions

• US 8,555,101 B2
• Filed: 03/11/2011
• Issued: 10/08/2013
• Est. Priority Date: 11/02/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ajanovic, Jasmin, Wagh, Mahesh, Sethi, Prashant, Das Sharma, Debendra, Harriman, David, Rosenbluth, Mark, Bhatt, Ajay, Barry, Peter, Rodgers, Scott Dion, Vasudevan, Anil, Muthrasanallur, Sridhar, Akiyama, James, Blankenship, Robert, Falik, Ohad, Mendelson, Abraham, Pardo, Ilan, Tamari, Eran, Weissmann, Eliezer, Shamia, Doron
• Primary Examiner(s): Stoynov, Stefan
• Application Number:
  US13/046,345
• Publication Number:
  US 20110161703A1
• Time in Patent Office: 942 Days
• Field of Search: 713/300, 713/320, 710/104, 710/105, 710/305, 455/574
• US Class Current: 713/330
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3253 Power saving in bus
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4265 on a point to point bus G06F13/4247, G06F13/4282 take precedence
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Claims

1. An apparatus comprising:

an input/output (I/O) device adapted to implement a layered protocol stack for communication on a serial interconnect, the I/O device including, receiving logic adapted to receive a power state request referencing a power state;

storage adapted to hold a referencing to the power state associated with a plurality of power sub-states; and

configuration logic adapted to select a power sub-state of the plurality of power sub-states based at least in part on an algorithm relating power consumption associated with the I/O device to a performance metric associated with the I/O device and to configure the I/O device according to specifications of the power sub-state in response to selecting the power sub-state.

2. The apparatus of claim 1, wherein the power state request reference a power state is also to reference a requested power sub-state or the plurality of power sub-states, and wherein the configuration logic is adapted to ignore the requested power sub-state and to select the power sub-state of the plurality of power sub-states based on the algorithm.

3. The apparatus of claim 1, wherein the algorithm relating power consumption associated with the I/O device to a performance metric associated with the I/O device further includes taking into account a transition latency between a current power state of the I/O device to the power sub-state of the I/O device.

4. The apparatus of claim 1, wherein the power state request is generated in response to an interrupt.

5. The apparatus of claim 1, wherein the layered protocol stack is adapted to adhere to specification requirements for a Peripheral Component Interconnect Express based interconnect layered stack.

6. A method comprising:

receiving a power state request referencing a power state with an input/output (I/O) device implementing a layered protocol stack for communication on a serial interconnect;

determining a plurality of power sub-states associated with the power state from storage within the I/O device; and

selecting a power sub-state of the plurality of power sub-states based at least in part on an algorithm relating power consumption associated with the I/O device to a performance metric associated with the I/O device; and

configuring hardware of the I/O device according to specifications of the power sub-state in response to selecting the power sub-state.

7. The method of claim 6, wherein the power state request reference a power state is also to reference a requested power sub-state or the plurality of power sub-states, and wherein selecting the power sub-state of the plurality of power sub-states based on the algorithm is performed without being limited to the request power sub-state.

8. The method of claim 6, wherein the algorithm relating power consumption associated with the I/O device to a performance metric associated with the I/O device further includes taking into account a transition latency between a current power state of the I/O device to the power sub-state of the I/O device.

9. The method of claim 6, wherein the power state request is generated in response to an interrupt.

10. The method of claim 6, wherein the layered protocol stack adheres to specification requirements for a Peripheral Component Interconnect Express based interconnect layered stack.