Memory system, memory system controller, and a data processing method in a host apparatus

• US 8,555,144 B2
• Filed: 11/14/2011
• Issued: 10/08/2013
• Est. Priority Date: 11/30/2004
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Aizawa, Hideo
• Primary Examiner(s): Baker, Stephen M
• Application Number:
  US13/295,891
• Publication Number:
  US 20120066569A1
• Time in Patent Office: 694 Days
• Field of Search: 714/773
• US Class Current: 714/773
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems

Abstract

A memory system includes code data generating section which generates code data based on write data. A nonvolatile semiconductor memory stores the write data and the code data for the write data and outputs read data and the code data for the read data. An error correcting section is configured to correct an error bit included in the read data using the read data and the code data for the read data, and outputs the read data which includes the error bit in accordance with a setting. An interface section receives the write data from outside of the memory system, and outputs the read data to outside of the memory system.

Claims

1. A memory system comprising:

a code data generating section which generates code data based on write data;

a nonvolatile semiconductor memory which stores the write data and the code data for the write data and outputs read data and the code data for the read data;

a signal pin;

an error correcting section which is configured to correct an error bit included in the read data using the read data and the code data for the read data;

an interface section which receives the write data, a read command and a mode control command from outside of the memory system, and outputs the read data to outside of the memory system, the read command and the mode control command received via the signal pin; and

a mode control section which sets the memory system in one of a first operation mode and a second operation mode based on the mode control command, wherein,

the interface section outputs the read data which is read from the nonvolatile semiconductor memory and includes an error bit to outside of the memory system in response to the read command in the first operation mode, and

the error correcting section corrects an error bit included in the read data read from the nonvolatile semiconductor memory and the interface section outputs the read data including the error bit corrected to outside of the memory system in response to the read command in the second operation mode.

2. The memory system according to claim 1, wherein, in a first operation mode, the interface section outputs the read data including the error bit corrected to outside of the memory system when the error correcting section is able to correct the error bit, and the interface section outputs the read data including the error bit to outside of the memory system without correcting the error bit when the error correcting section is not able to correct the error bit.

3. The memory system according to claim 1, wherein, when the error correcting section is not able to correct the error bit, the interface section outputs the read data including the error bit and an error information signal indicating that the read data includes the error bit to outside of the memory system without correcting the error bit.

4. The memory system according to claim 1, wherein, in a second operation mode, the interface section outputs the read data including the error bit corrected to outside of the memory system when the error correcting section is able to correct the error bit, and the interface section does not output the read data to outside of the memory system when the error correcting section is not able to correct the error bit.

5. The memory system according to claim 1, wherein the signal pin is a command pin.

6. The memory system according to claim 1 further comprising:

a controller which manages a correspondence between a logical block address and a physical block address.

7. The memory system according to claim 1, wherein,

the error correcting section is normally set in a second operation mode,

the interface section outputs the read data including the error bit corrected to outside of the memory system when the error correcting section is able to correct the error bit in the second operation mode, and

the interface section does not output the read data to outside of the memory system when the error correcting section is not able to correct the error bit in the second operation mode.

8. The memory system according to claim 7, wherein, when a period in which the interface section does not output the read data exceeds a set period in the second operation mode, the error correcting section is set to the first operation mode.

9. A memory system controller which controls a nonvolatile semiconductor memory mounted in a memory system, comprising:

a code data generating section which generates code data based on write data;

a signal pin;

an error correcting section which is configured to correct an error bit included in read data using the read data and the code data for the read data which is read from the nonvolatile semiconductor memory;

an interface section which receives the write data, a read command and a mode control command from outside of the memory system, and outputs the read data to outside of the memory system, the read command and the mode control command received via the signal pin; and

a mode control section which sets the memory system in one of a first operation mode and a second operation mode based on the mode control command, wherein,

the interface section outputs the read data which is read from the nonvolatile semiconductor memory and includes an error bit to outside of the memory system in response to the read command in the first operation mode, and

the error correcting section corrects an error bit included in the read data read from the nonvolatile semiconductor memory and the interface section outputs the read data including the error bit corrected to outside of the memory system in response to the read command in the second operation mode.

10. The memory system controller according to claim 9, wherein, in a first operation mode, the interface section outputs the read data including the error bit corrected to outside of the memory system controller when the error correcting section is able to correct the error bit, and the interface section outputs the read data including the error bit to outside of the memory system controller without correcting the error bit when the error correcting section is not able to correct the error bit.

11. The memory system controller according to claim 9, wherein, when the error correcting section is not able to correct the error bit, the interface section outputs the read data including the error bit and an error information signal indicating that the read data includes the error bit to outside of the memory system controller without correcting the error bit.

12. The memory system controller according to claim 9, wherein, in a second operation mode, the interface section outputs the read data including the error bit corrected to outside of the memory system controller when the error correcting section is able to correct the error bit, and the interface section does not output the read data to outside of the memory system controller when the error correcting section is not able to correct the error bit.

13. The memory system controller according to claim 9, wherein the signal pin is a command pin.

14. The memory system controller according to claim 9, wherein the memory system controller manages a correspondence between a logical block address and a physical block address.

15. The memory system controller according to claim 9, wherein,

the error correcting section is normally set in a second operation mode,

the interface section outputs the read data including the error bit corrected to outside of the memory system controller when the error correcting section is able to correct the error bit in the second operation mode, and

the interface section does not output the read data to outside of the memory system controller when the error correcting section is not able to correct the error bit in the second operation mode.

16. The memory system controller according to claim 15, wherein, when a period in which the interface section does not output the read data exceeds a set period in the second operation mode, the error correcting section is set to the first operation mode.

17. A data processing method in a host apparatus into which a memory system is inserted, the memory system comprising a nonvolatile semiconductor memory and a memory system controller controlling the nonvolatile semiconductor memory, the method comprising:

providing the memory system with a mode control command which sets the memory system in one of a first operation mode and a second operation mode via a signal pin of the memory system;

generating code data based on write data;

instructing the memory system to write the write data and the code data for the write data into the nonvolatile semiconductor memory;

instructing the memory system to read read data and the code data for the read data from the nonvolatile semiconductor memory with a read command transmitted via the signal pin;

judging an operation mode of the memory system; and

correcting an error bit included in the read data using the read data and the code data for the read data when the operation mode is the first operation mode, wherein,

the read data which is read from the nonvolatile semiconductor memory and includes an error bit is output from the memory system in response to a read command received from the host apparatus to the memory system via the signal pin in the first operation mode, and

an error bit included in the read data read from the nonvolatile semiconductor memory is corrected and the read data including the error bit corrected is output from the memory system in response to a read command received from the host apparatus to the memory system via the signal pin in the second operation mode.

18. The data processing method according to claim 17, wherein setting the operation mode of the memory system and instructing the memory system to read read data and the code data for the read data from the nonvolatile semiconductor memory are carried out by one command.

19. The data processing method according to claim 17, further comprising:

instructing the memory system to take the second operation mode in which the memory system outputs the read data and the code data for the read data without correcting the error bit when the host apparatus does not receive the read data and the code data for the read data before a predetermined time elapses after the host apparatus instructs the memory system to output the read data and the code data for the read data; and

instructing the memory system to read the read data and the code data for the read data from the nonvolatile semiconductor memory again.