Microchips with an internal hardware firewall

• US 8,555,370 B2
• Filed: 08/24/2012
• Issued: 10/08/2013
• Est. Priority Date: 11/29/1996
• Status: Expired due to Fees

• Current Assignee: Frampton E. Ellis
• Original Assignee: Frampton E. Ellis
• Inventors: Ellis, Frampton E
• Primary Examiner(s): Reza, Mohammad W
• Application Number:
  US13/594,614
• Publication Number:
  US 20120324563A1
• Time in Patent Office: 410 Days
• Field of Search: 726/11, 726/12, 726/13, 726/14, 713/100, 713/151, 713/153, 713/154
• US Class Current: 726/11
• CPC Class Codes: A01N 25/30 characterised by the surfactants
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/2035 without idle spare hardware
• CPC Class Codes: G06F 11/2043 where the redundant components share a common memory address space
• CPC Class Codes: G06F 15/76 Architectures of general purpose stored program computers with program plugboard G06F15/08; multicomputers G06F15/16
• CPC Class Codes: G06F 21/00 Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
• CPC Class Codes: G06F 9/5072 Grid computing
• CPC Class Codes: H04L 43/00 Arrangements for monitoring or testing data switching networks
• CPC Class Codes: H04L 63/02 for separating internal from external traffic, e.g. firewalls
• CPC Class Codes: H04L 63/0209 Architectural arrangements, e.g. perimeter networks or demilitarized zones
• CPC Class Codes: H04L 67/10 in which an application is distributed across nodes in the network software deployment G06F8/60; multiprogramming arrangements G06F9/46
• CPC Class Codes: H04L 69/14 Multichannel or multilink protocols
• CPC Class Codes: H04L 69/329 in the application layer [OSI layer 7]
• CPC Class Codes: H04L 9/40 Network security protocols
• CPC Class Codes: Y04S 40/00 Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them

Abstract

A microchip for a computer configured to connect to at least one network of computers. The microchip includes at least a first internal hardware firewall configured to deny access to at least a first protected portion of said microchip from said network, and at least one general purpose microprocessor including at least two general purpose core or general purpose processing units. At least a first core or processing unit is located within the first protected portion of the microchip. At least a second core or processing unit is located within a second portion of the microchip that is not protected by at least said first internal hardware firewall. At least the second core or processing unit is separated from the first core or processing unit by at least the first internal hardware firewall and is located between at least the first internal hardware firewall and the at least one network.

Claims

1. A microchip for a computer configured to connect to at least one network of computers, said microchip comprising:

at least a first internal hardware firewall configured to deny access to at least a first protected portion of said microchip from said network;

at least one general purpose microprocessor including at least two general purpose core or general purpose processing units, and wherein

at least a first said core or processing unit is located within said first protected portion of said microchip that is protected by at least said first internal hardware firewall;

at least a second said core or processing unit is located within a second portion of said microchip that is not protected by at least said first internal hardware firewall; and

at least said second core or processing unit is separated from said first core or processing unit by at least said first internal hardware firewall and is located between at least said first internal hardware firewall and said at least one network of computers.

2. The microchip of claim 1, wherein said microchip is surrounded by at least one Faraday Cage.

3. The microchip of claim 2, wherein said microchip comprises a plurality of Faraday Cages.

4. The microchip of claim 1, wherein said microchip comprises a plurality of dies, at least two of said dies having been made by a separate fabrication process and assembled into a package with separate die sections connected directly.

5. The microchip of claim 1, further comprising a master control unit of the microprocessor located within said first protected portion of said microchip that is protected by at least said first internal hardware firewall, and said master control unit is configured to control said second said core or processing unit.

6. The microchip of claim 5, wherein said microchip includes at least three or more said cores or processing units, each located within a portion of said microchip unprotected by at least said first internal hardware firewall and each controlled by the master control unit.

7. The microchip of claim 6, wherein the master control unit of the microprocessor is also protected by a second said internal hardware firewall.

8. The microchip of claim 6, further comprising at least one memory component associated with at least one said core or processing unit, said memory component being protected by at least a second said internal hardware firewall that is located between said memory component and said at least one said core or processing unit with which said memory component is associated.

9. A microchip for a computer configured to connect to at least one network of computers, said microchip comprising:

at least four internal hardware firewalls, said at least four internal hardware firewalls configured to deny access to at least four protected portions of said microchip from said network of computers;

at least one general purpose microprocessor with at least four general purpose cores or general purpose processing units;

each of at least three of said cores or said processing units is located within a different one of said four protected portions of said microchip protected by one of at least three of said at least four internal hardware firewalls; and

at least a fourth said core or said processing unit is located within a portion of said microchip that is not protected by said at least said three of said at least four internal hardware firewalls, at least said fourth core or processing unit is separated from said first core or processing unit by at least said three of said at least four internal hardware firewalls and is located between said three of said at least four internal hardware firewalls and said at least one network of computers;

at least one memory component associated with at least one said core or processing unit and located within at least one said protected portion of said microchip that is protected by at least said fourth said internal hardware firewall located between said memory component and said at least one said core or processing unit with which said memory component is associated; and

a master control unit of the microprocessor located within at least one said protected portion of said microchip that is protected by at least one said internal hardware firewall, and said master control unit is configured to control said cores or processing units.

10. The microchip of claim 9, wherein said microchip is surrounded by at least one Faraday Cage.

11. The microchip of claim 10, wherein said microchip comprises a plurality of Faraday Cages.

12. The microchip of claim 9, wherein said microchip comprises a plurality of dies, at least two of said dies having been made by a separate fabrication process and assembled into a package with separate die sections connected directly.

13. A microchip for a computer configured to connect to at least one network of computers, said microchip comprising:

at least a first internal hardware firewall, said first internal hardware firewall configured to deny access to at least a protected portion of said microchip from said network;

at least one general purpose microprocessor with at least a general purpose core or processing unit including a master control unit of the microprocessor and at least one general purpose core or general purpose processing unit; and

wherein

at least the general purpose core or processing unit including said master control unit is located within the protected portion of said microchip that is protected by at least said first internal hardware firewall;

at least a second said core or processing unit is located within a portion of said microchip that is not protected by at least said first internal hardware firewall and said master control unit is configured to control said at least said second core or processing unit; and

at least said second core or processing unit is separated from said first core or processing unit by said first internal hardware firewall and is located between said first internal hardware firewall and said at least one network of computers.

14. The microchip of claim 13, where said microchip is surrounded by a Faraday Cage.

15. The microchip of claim 13, wherein said microchip comprises a plurality of Faraday Cages.

16. The microchip of claim 13, wherein said microchip includes three or more said internal hardware firewalls.

17. The microchip of claim 13, wherein said microchip comprises a plurality of dies, at least two of said dies having been made by a separate fabrication process and assembled into a package with separate die sections connected directly.

18. The microchip of claim 15, wherein said microchip includes at least three or more said cores or processing units, each located within at least one said protected portion of said microchip that is protected by at least one said internal hardware firewall.

19. The microchip of claim 18, wherein said microchip includes three or more said internal hardware firewalls.

20. The microchip of claim 13, further comprising at least one memory component associated with at least one said core or processing unit, said memory component being protected by at least a second internal hardware firewall that is located between said memory component and said at least one said core or processing unit with which said memory component is associated.