Method for packaging circuits

• US 8,555,495 B2
• Filed: 11/17/2011
• Issued: 10/15/2013
• Est. Priority Date: 05/06/2003
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Chia, Yong Poo, Waf, Low Siu, Boon, Suan Jeung, Koon, Eng Meow, Chua, Swee Kwang
• Primary Examiner(s): Nguyen, Donghai D.
• Application Number:
  US13/299,120
• Publication Number:
  US 20120064697A1
• Time in Patent Office: 698 Days
• Field of Search: 29830-832, 298/34, 298/40, 298/41, 298/46, 29851-853, 294/15, 174/254, 174/256, 174/260, 174/262, 257/684, 257/686, 257/698, 361/760, 361/783, 361/820, 438/109
• US Class Current: 29/853
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 22/00 Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06548 Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06558 the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
• CPC Class Codes: H01L 2225/06575 Auxiliary carrier between devices, the carrier having no electrical connection structure
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: Y10T 29/49128 : Assembling formed circuit to base
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49144 : by metal fusion
• CPC Class Codes: Y10T 29/49146 : with encapsulating, e.g., potting, etc.
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base
• CPC Class Codes: Y10T 29/49167 : with deforming of conductive path
• CPC Class Codes: Y10T 29/49169 : Assembling electrical component directly to terminal or elongated conductor
• CPC Class Codes: Y10T 29/49794 : Dividing on common outline

Abstract

A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.

Claims

1. A method comprising:

curing adhesive to fix a first substrate to a second substrate, and to align first saw streets separating a plurality of first dice on the first substrate with second saw streets separating a plurality of second dice on the second substrate;

cutting a kerf through the first substrate in the first saw streets;

removing exposed adhesive between at least some of the plurality of first dice;

lazing the second saw street to form through holes;

forming electrical connections from the first dice on the first substrate to the second dice on the second substrate through the through holes; and

singulating aligned first and second dice from a remainder of the fixed first and second substrates.

2. The method of claim 1, wherein removing the exposed adhesive between at least some of the plurality of first dice includes chemically etching the exposed adhesive.

3. The method of claim 1, wherein forming the electrical connections includes forming a metal trace from a bond pad of the first dice to a bond pad of the second dice through at least one of the through holes.

4. The method of claim 1, wherein singulating the aligned first and second dice includes mechanically cutting the aligned first and second saw streets.

5. The method of claim 4, wherein singulating the aligned first and second dice includes exposing at least one of the electrical connections along a side of the fixed first and second substrates.

6. The method of claim 1, wherein the curing includes curing the adhesive disposed between a base surface of the first substrate and a base surface of the second substrate, wherein respective active device surfaces of the first and second substrates are exposed, the active device surface of each of the first and second substrates being oppositely disposed from the respective base surface of each of the first and second substrates.

7. The method of claim 1, wherein forming the electrical connections includes filling at least some of the through holes with a conductive material.

8. The method of claim 1, wherein singulating the aligned first and second dice includes forming the electrical connections to be substantially flush with smooth sides of the singulated aligned first and second dice.

9. A method comprising:

curing adhesive to fix a first substrate to a second substrate, and to align first saw streets separating a plurality of first dice on the first substrate with second saw streets separating a plurality of second dice on the second substrate;

cutting through the first substrate along the first saw streets of the first substrate;

removing exposed adhesive between at least some of the plurality of first dice;

cutting through the second saw street to form through holes;

forming electrical connections from the first dice on the first substrate to the second dice on the second substrate through the through holes; and

singulating aligned first and second dice from a remainder of the fixed first and second substrates.

10. The method of claim 9, wherein cutting through the first substrate includes cutting a trench in the first substrate.

11. The method of claim 9, wherein cutting through the first substrate includes cutting a kerf in the first substrate.

12. The method of claim 9, wherein cutting through the second saw street includes lazing the second saw street.

13. The method of claim 9, wherein cutting through the second saw street includes using an excimer laser to cut through the second saw street.

14. The method of claim 9, wherein cutting through the second saw street includes using a solid state laser to cut through the second saw street.

15. The method of claim 9, wherein forming the electrical connections includes filling one or more of the through holes with a conductive material.

16. The method of claim 9, wherein singulating the aligned first and second dice includes forming substantially smooth sides of the singulated aligned first and second dice with the electrical connections being substantially flush with the substantially smooth sides.

17. A method comprising:

curing adhesive to fix a first substrate to a second substrate, and to align first saw streets separating a plurality of first dice on the first substrate with second saw streets separating a plurality of second dice on the second substrate;

cutting a kerf in the first saw streets of the first substrate through the first substrate;

removing exposed adhesive between at least some of the plurality of first dice;

lazing the second saw street to form through holes;

forming electrical connections from the first dice on the first substrate to the second dice on the second substrate through the through holes, wherein forming the electrical connections includes filling at least some of the through holes with a conductive material; and

singulating aligned first and second dice from a remainder of the fixed first and second substrates, forming the electrical connections to be substantially flush with smooth sides of the singulated aligned first and second dice.

18. The method of claim 17, wherein lazing the second saw street includes using an excimer laser to cut through the second saw street.

19. The method of claim 17, wherein lazing the second saw street includes using a solid state laser to cut through the second saw street.

20. The method of claim 17, wherein removing the exposed adhesive includes using chemical etching to remove the exposed adhesive from between at least some of the plurality of first dice.