Method for fabrication of a semiconductor device and structure

• US 8,557,632 B1
• Filed: 04/09/2012
• Issued: 10/15/2013
• Est. Priority Date: 04/09/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak C., Cronquist, Brian
• Primary Examiner(s): Blum, David S
• Application Number:
  US13/441,923
• Publication Number:
  US 20130267046A1
• Time in Patent Office: 554 Days
• Field of Search: 438/107, 257/E21.499, 257/E23.145
• US Class Current: 438/107
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/66272 Silicon vertical transistors H01L29/66242, H01L29/66257 and H01L29/66265 take precedence
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66901 with a PN homojunction gate
• CPC Class Codes: H01L 29/732 Vertical transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/808 : with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H10B 12/09 : with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 63/30 : comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/845 : the switching components being connected to a common vertical conductor

Abstract

A method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a first metal layer overlaying the first transistors and providing at least one connection to the first transistors, then processing a second metal layer overlaying the first metal layer, then processing a second layer of second transistors overlaying the second metal layer, wherein the second metal layer is connected to provide power to at least one of the second transistors.

Claims

1. A method to process an Integrated Circuit device comprising:

processing a first layer of first transistors, then

processing a first metal layer overlaying said first transistors and providing at least one connection to said first transistors, then

processing a second metal layer overlaying said first metal layer, then

processing a second layer of second transistors overlaying said second metal layer, wherein

said second metal layer is connected to provide power to at least one of said second transistors.

2. A method according to claim 1, comprising said second transistors forming logic cells, wherein

at least one of said logic cells comprises a connection made by said second metal layer.

3. A method according to claim 1, wherein

said second metal layer comprises a plurality of routing structures connecting between a plurality of said second transistors.

4. A method according to claim 1, comprising forming a connection path between said second transistors and said second metal layer, wherein

said connection path comprises at least one through-layer via, and wherein said through-layer via comprises material whose co-efficient of thermal expansion is within 50 percent of a coefficient of thermal expansion of said second layer.

5. A method according to claim 1, comprising a process forming high quality oxide isolation between said second transistors using radical oxidation or a high density plasma deposition.

6. A method according to claim 1, wherein said first layer comprises a first alignment mark, and comprises forming at least one via through said second layer, wherein said forming at least one via comprises alignment at least partially to said first alignment mark.

7. A method according to claim 1, comprises forming at least one via through said second layer, wherein said at least one via is adapted to conduct heat.

8. A method to process an Integrated Circuit device comprising:

processing a first layer of first transistors, then

processing a first metal layer overlaying said first transistors and providing at least one connection to said first transistors, then

processing a second metal layer overlaying said first metal layer, then

processing a second layer of second transistors overlaying said second metal layer, then processing a third metal layer overlying said second transistors, wherein at least one of said second transistors is provided with a back-bias.

9. A method according to claim 8, comprising forming at least one via through said second layer, wherein said at least one via is adapted to conduct heat.

10. A method according to claim 8, wherein

said second metal layer is connected to provide power to at least one of said second transistors.

11. A method according to claim 8, comprising forming a connection path between said second transistors and said second metal layer, wherein

said connection path comprises at least one through-layer via, and wherein said through-layer via comprises material whose co-efficient of thermal expansion is within 50 percent of a coefficient of thermal expansion of said second layer.

12. A method according to claim 8, comprising a process forming high quality oxide isolation between said second transistors using radical oxidation or a high density plasma deposition.

13. A method according to claim 8, wherein said first layer comprises a first alignment mark, and comprises forming at least one via through said second layer, wherein said forming at least one via comprises alignment at least partially to said first alignment mark.

14. A method according to claim 8, comprising forming at least one via through said second layer, wherein said at least one via is forming a direct contact with at least one of said second transistors.

15. A method according to claim 8, wherein at least one of said second transistors is one of:

(i) a replacement-gate transistor;

(ii) a Finfet transistor;

or

(iii) a double gate horizontally oriented transistor.

16. A method to process an Integrated Circuit device comprising:

processing a first layer of first transistors, then

processing a first metal layer overlaying said first transistors and providing at least one connection to said first transistors, then

processing a second metal layer overlaying said first metal layer, then

processing a second layer of second transistors overlaying said second metal layer, comprising

forming at least one connection path between said second transistors and said second metal layer, wherein

said connection path comprises at least one through-layer via, and wherein said through-layer via comprises material whose co-efficient of thermal expansion is within 50 percent of a coefficient of thermal expansion of said second layer.

17. A method according to claim 16, wherein

said second metal layer comprises a power grid to provide power to at least one of said second transistors.

18. A method according to claim 16, comprising a process forming high quality oxide isolation between said second transistors using radical oxidation or a high density plasma deposition.

19. A method according to claim 16, wherein said first layer comprises a first alignment mark, and comprises forming at least one via through said second layer, wherein said forming at least one via comprises alignment at least partially to said first alignment mark.

20. A method according to claim 16, comprises forming at least one via through said second layer, wherein said at least one via comprises tungsten.

21. A method according to claim 16 wherein said second metal layer comprises mostly copper or aluminum.

22. A method according to claim 16, wherein at least one of said second transistors is one of:

(i) a replacement-gate transistor;

(ii) a Finfet transistor;

or

(iii) a double gate horizontally oriented transistor.

23. A method according to claim 16, comprising;

back-bias for at least one of said second transistors.

24. A method to process an Integrated Circuit device comprising:

processing a first layer of first transistors, then

processing a first metal layer overlaying said first transistors and providing at least one connection to said first transistors, then

processing a second metal layer overlaying said first metal layer, then

processing a second layer of second transistors overlaying said second metal layer, then

processing a third metal layer overlying said second transistors,

wherein at least one of said second transistors is one of;

(i) a replacement-gate transistor;

(ii) a Finfet transistor;

or

(iii) a double gate horizontally oriented transistor.

25. A method according to claim 24, comprising;

back-bias for at least one of said second transistors.

26. A method according to claim 24, wherein said second metal layer is connected to provide power to at least one of said second transistors.

27. A method according to claim 24, comprising forming a connection path between said second transistors and said first transistors, wherein

said connection path comprises at least one through-layer via, and wherein said through-layer via comprises material whose co-efficient of thermal expansion is within 50 percent of a coefficient of thermal expansion of said second layer.

28. A method according to claim 24, comprising a process forming high quality oxide isolation between said second transistors using radical oxidation or a high density plasma deposition.

29. A method according to claim 24, wherein said first single crystal layer comprises a first alignment mark, and comprises forming at least one via through said second layer, wherein said forming at least one via comprises alignment at least partially to said first alignment mark.

30. A method according to claim 24, comprising

vias through said second layer wherein said vias are adapted to conduct heat.