Method of manufacturing a semiconductor device using an etchant

• US 8,557,651 B2
• Filed: 03/04/2011
• Issued: 10/15/2013
• Est. Priority Date: 03/04/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Hyo-San, Yoon, Bo-Un, Lee, Kun-Tack, Cho, Hag-Ju, Hyun, Sang-Jin, Na, Hoon-Joo, Hong, Hyung-Seok
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): JUNGE, BRYAN R.
• Application Number:
  US13/040,472
• Publication Number:
  US 20110217833A1
• Time in Patent Office: 956 Days
• Field of Search: 438/216, 438/275, 438/287, 438/591, 257/324, 257/325, 257/392, 257/406, 257/410, 257/411
• US Class Current: 438/216
• CPC Class Codes: H01L 21/28 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268 etching for patterning the electrodes H01L21/311, H01L21/3213; multistep manufacturing processes for data storage electrodes H01L29/4011
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

In an etchant for etching a capping layer having etching selectivity with respect to a dielectric layer, the capping layer changes compositions of the dielectric layer, to thereby control a threshold voltage of a gate electrode including the dielectric layer. The etchant includes about 0.01 to 3 percent by weight of an acid, about 10 to 40 percent by weight of a fluoride salt and a solvent. Accordingly, the dielectric layer is prevented from being damaged by the etching process for removing the capping layer and the electric characteristics of the gate electrode are improved.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a dielectric layer on a substrate having a first region and a second region;

forming a capping layer on the dielectric layer; and

forming a capping layer pattern by selectively etching the capping layer using an etchant from one of the first and the second regions of the substrate, the etchant including about 0.01 to 0.18 percent by weight of an acid, about 10 to 40 percent by weight of a fluoride salt, and a solvent.

2. The method of claim 1, wherein the dielectric layer includes any one material selected from the group consisting of hafnium oxide (HfOx), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO), titanium oxide (TiOx), aluminum titanium oxide (AlTiO) and combinations thereof.

3. The method of claim 2, wherein the dielectric layer has a dielectric constant of at least about 10.

4. The method of claim 1, wherein the capping layer is etched at an etch rate at least 3 times greater than the etch rate of the dielectric layer.

5. The method of claim 4, wherein the etchant has an etch selectivity with respect to the dielectric layer such that the capping layer is etched at an etch rate at least 5 times greater than the dielectric layer.

6. The method of claim 5, wherein the etchant has an etch selectivity with respect to the dielectric layer such that the capping layer is etched at an etch rate at least 10 times greater than the dielectric layer.

7. The method of claim 1, wherein the etchant further includes about 0.01 to about 1 percent by weight of a surfactant.

8. The method of claim 1, wherein the acid includes any one selected from the group consisting of hydrochloric acid, sulfuric acid, nitric acid and phosphoric acid, fluoric acid and combinations thereof.

9. The method of claim 1, wherein the fluoride salt includes any one selected from the group consisting of potassium difluoride (KHF₂), ammonium fluoride (NH₄F), ammonium difluoride (NH₄HF₂), hydrogen fluoride pyridine and combinations thereof.

10. The method of claim 1, further comprising changing a composition of the dielectric layer underlying the capping layer pattern by a heat treatment to the capping layer pattern at one of the first and the second regions of the substrate, so that the dielectric layer includes a first dielectric layer of which the composition is unchanged at the first region of the substrate and a second dielectric layer of which the composition is changed by the heat treatment at the second region of the substrate.

11. The method of claim 10, wherein the composition of the second dielectric layer is changed by one of permeation from the capping layer pattern and reaction with the capping layer pattern.

12. The method of claim 11, further comprising:

removing the capping layer pattern from the second dielectric layer;

forming a gate electrode layer on the first and the second dielectric layers, the gate electrode layer including a metal nitride; and

sequentially patterning the gate electrode layer, the first and the second dielectric layers, thereby forming a first gate structure on the first region of the substrate and a second gate structure on the second region of the substrate.

13. The method of claim 12, further comprising an insulation interlayer on the substrate, the insulation interlayer including a plurality of openings through which the substrate is partially exposed, wherein the first and the second gate structures are formed in the openings, respectively.

14. The method of claim 12, wherein the first region includes an NMOS region on which an N-channel MOS transistor is formed and the second region includes a PMOS region on which a P-channel MOS transistor is formed, and the capping layer includes any one material selected from the group consisting of aluminum nitride, aluminum oxide, dysprosium oxide, lanthanum oxide, silicon oxide and combinations thereof, so that the capping layer in the NMOS region is selectively removed and the capping layer pattern is formed in the PMOS region.

15. The method of claim 12, wherein the first region includes an NMOS region on which an N-channel MOS transistor is formed and the second region includes a PMOS region on which a P-channel MOS transistor is formed, and the capping layer includes lanthanum oxide, so that the capping layer in the PMOS region is selectively removed and the capping layer pattern is formed in the NMOS region.

16. The method of claim 1, further comprising, before forming the capping layer pattern, forming a photoresist pattern on the capping layer at one of the first and the second regions of the substrate.

17. The method of claim 16, further comprising:

removing the photoresist pattern from the capping layer pattern; and

changing a composition of the dielectric layer under the capping layer pattern by a heat treatment to the capping layer pattern at one of the first and the second regions of the substrate.

18. The method of claim 1, before forming the dielectric layer, further comprising forming an interface layer on the substrate, the interface layer including a material having a dielectric constant smaller than about 4.

19. The method of claim 1, wherein the capping layer includes one or more of aluminum nitride (AlNx), aluminum oxide (AlOx), dysprosium oxide (DyOx), and silicon oxide (SiOx).