Semiconductor wafer-to-wafer bonding for dissimilar semiconductor dies and/or wafers

• US 8,557,680 B2
• Filed: 07/10/2012
• Issued: 10/15/2013
• Est. Priority Date: 08/26/2009
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Chandrasekaran, Arvind, Henderson, Brian M.
• Primary Examiner(s): Sefer, A.
• Application Number:
  US13/545,393
• Publication Number:
  US 20120276716A1
• Time in Patent Office: 462 Days
• Field of Search: 438/109, 438/458, 257/235
• US Class Current: 438/458
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2221/68331 of passive members, e.g. die mounting substrate
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/14051 Bump connectors having different shapes
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16148 the bump connector connecting to a bonding area protruding from the surface
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81193 wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/838 : Bonding techniques
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/18165 : of a wire bonded chip

Abstract

A process for wafer-to-wafer bonding of a first wafer having a first set of dies of a first die size to a reconstituted wafer of a second set of dies having a second die size different than the first die size. The process includes aligning the second set of dies such that a second set of interconnects on the second set of dies aligns with a first set of interconnects on the first set of dies. The second set of dies includes a spacing between the second set of dies based on parameters of the first set of dies. The process also includes coupling the reconstituted wafer with the first wafer to create a wafer stack.

Claims

1. A semiconductor manufacturing process for wafer-to-wafer bonding of a first wafer having a first plurality of dies of a first die size to a reconstituted wafer having a second plurality of dies of a second die size different than the first die size, the process comprising:

aligning the second plurality of dies, having a spacing between the second plurality of dies based on parameters of the first plurality of dies, such that a second plurality of interconnects on the second plurality of dies aligns with a first plurality of interconnects on the first plurality of dies; and

coupling the reconstituted wafer with the first wafer to create a wafer stack.

2. The process of claim 1, further comprising:

singulating the second plurality of dies from a third wafer before aligning the second plurality of dies; and

molding the singulated second plurality of dies into the reconstituted wafer.

3. The process of claim 2, further comprising:

singulating a third die from a fourth wafer; and

molding the third die into the reconstituted wafer.

4. The process of claim 3, further comprising arranging the third die proximate to a second die of the second plurality of dies such that the third die overlaps with a first portion of a first die of the first plurality of dies and the second die of the second plurality of dies overlaps with a second portion of the first die before molding.

5. The process of claim 2, in which singulating the second plurality of dies from the third wafer comprises singulating the second plurality of dies from the third wafer of different size than the first wafer.

6. The process of claim 1, in which the first wafer is substantially a same size as the reconstituted wafer.

7. The process of claim 1, further comprising stacking at least one additional wafer on the wafer stack.

8. The process of claim 7, in which the at least one additional wafer comprises another reconstituted wafer.

9. The process of claim 1, in which a second die of the second plurality of dies comprises multiple tiers.

10. The process of claim 9, in which the second die comprises a vertically stacked memory device.

11. The process of claim 1 further comprising integrating the wafer stack into a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and/or a computer.

12. A semiconductor manufacturing process for wafer-to-wafer bonding of a first wafer having a first plurality of dies of a first die size to a reconstituted wafer having a second plurality of dies of a second die size different than the first die size, the process comprising:

step for aligning the second plurality of dies, having a spacing between the second plurality of dies based on parameters of the first plurality of dies, such that a second plurality of interconnects on the second plurality of dies aligns with a first plurality of interconnects on the first plurality of dies; and

step for coupling the reconstituted wafer with the first wafer to create a wafer stack.

13. The process of claim 12, further comprising:

step for singulating the second plurality of dies from a third wafer before aligning the second plurality of dies.

14. The process of claim 13, further comprising:

step for molding the singulated second plurality of dies into the reconstituted wafer.

15. The process of claim 14, further comprising:

step for singulating a third die from a fourth wafer; and

step for molding the third die into the reconstituted wafer.

16. The process of claim 15, further comprising:

step for arranging the third die proximate to a second die of the second plurality of dies such that the third die overlaps with a first portion of a first die of the first plurality of dies and the second die of the second plurality of dies overlaps with a second portion of the first die of the first plurality of dies before molding.

17. The process of claim 13, further comprising:

step for singulating the second plurality of dies from the third wafer by singulating the second plurality of dies from the third wafer of different size than the first wafer.

18. The process of claim 12, further comprising:

step for stacking at least one additional wafer on the water stack.

19. The process of claim 18 in which the at least one additional wafer comprises another reconstituted wafer.

20. The process of claim 12, further comprising:

step for integrating the wafer stack into a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and/or a computer.