Semiconductor device and manufacturing method of the same
First Claim
1. A semiconductor device comprising:
- a substrate;
a gate electrode layer over the substrate;
a gate insulating layer over the gate electrode layer;
a source electrode layer over the gate insulating layer;
a drain electrode layer over the gate insulating layer;
a semiconductor layer comprising indium and zinc over the source electrode layer, the drain electrode layer and the gate insulating layer, wherein the semiconductor layer is in contact with part of the gate insulating layer;
a pixel electrode layer electrically connected to one of the source electrode layer and the drain electrode layer; and
an EL layer over the pixel electrode layer,wherein the semiconductor layer comprises a channel region, andwherein the gate electrode layer is electrically connected to a wiring through a contact hole provided in the gate insulating layer.
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Abstract
The manufacturing method of the present invention includes steps of selectively forming a photocatalyst material or a material including an amino group by discharging a composition including the photocatalyst material or the material including an amino group; immersing the photocatalyst material or the material including an amino group in a solution including a plating catalyst material so as to adsorb or deposit the plating catalyst material onto the photocatalyst material or the material including an amino group; and immersing the plating catalyst material in a plating solution including a metal material so as to form a metal film on a surface of the photocatalyst material or the material including an amino group adsorbing or depositing the plating catalyst material, thereby manufacturing a semiconductor device. The pH of the solution including the plating catalyst material is adjusted in a range of 3 to 6.
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Citations
18 Claims
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1. A semiconductor device comprising:
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a substrate; a gate electrode layer over the substrate; a gate insulating layer over the gate electrode layer; a source electrode layer over the gate insulating layer; a drain electrode layer over the gate insulating layer; a semiconductor layer comprising indium and zinc over the source electrode layer, the drain electrode layer and the gate insulating layer, wherein the semiconductor layer is in contact with part of the gate insulating layer; a pixel electrode layer electrically connected to one of the source electrode layer and the drain electrode layer; and an EL layer over the pixel electrode layer, wherein the semiconductor layer comprises a channel region, and wherein the gate electrode layer is electrically connected to a wiring through a contact hole provided in the gate insulating layer. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A semiconductor device comprising:
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a substrate; a gate electrode layer over the substrate; a gate insulating layer over the gate electrode layer; a source electrode layer over the gate insulating layer; a drain electrode layer over the gate insulating layer; a semiconductor layer comprising zinc, oxide, indium and gallium over the source electrode layer, the drain electrode layer and the gate insulating layer, wherein the semiconductor layer is in contact with part of the gate insulating layer; a pixel electrode layer electrically connected to one of the source electrode layer and the drain electrode layer; and an EL layer over the pixel electrode layer, wherein the semiconductor layer comprises a channel region, and wherein the gate electrode layer is electrically connected to a wiring through a contact hole provided in the gate insulating layer. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A semiconductor device comprising:
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a substrate; a gate electrode layer over the substrate; a gate insulating layer over the gate electrode layer; a source electrode layer over the gate insulating layer; a drain electrode layer over the gate insulating layer; a semiconductor layer comprising zinc, oxide and indium or gallium over the source electrode layer, the drain electrode layer and the gate insulating layer, wherein the semiconductor layer is in contact with part of the gate insulating layer; a pixel electrode layer electrically connected to one of the source electrode layer and the drain electrode layer; and an EL layer over the pixel electrode layer, wherein the semiconductor layer comprises a channel region, and wherein the gate electrode layer is electrically connected to a wiring through a contact hole provided in the gate insulating layer. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification