Sawtooth electric field drift region structure for power semiconductor devices

• US 8,558,275 B2
• Filed: 12/31/2007
• Issued: 10/15/2013
• Est. Priority Date: 12/31/2007
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bobde, Madhur
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): SALERNO, SARAH KATE
• Application Number:
  US12/006,399
• Publication Number:
  US 20090166672A1
• Time in Patent Office: 2,115 Days
• Field of Search: 257/E29.027, 257/E29.006, 257/E29.197, 257/E31.382, 257/262, 257/197, 257/273, 257/361, 257/362, 257/329, 257/E21.382, 257/139, 257/E29.005, 257/E29.012
• US Class Current: 257/139
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/66128 Planar diodes
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes

Abstract

This invention discloses a semiconductor power device formed in a semiconductor substrate. The semiconductor power device further includes rows of multiple horizontal columns of thin layers of alternate conductivity types in a drift region of the semiconductor substrate where each of the thin layers having a thickness to enable a punch through the thin layers when the semiconductor power device is turned on. In a specific embodiment the thickness of the thin layers satisfying charge balance equation q*N_D*W_N=q*N_A*W_P and a punch through condition of W_P<2*W_D*[N_D/(N_A+N_D)] where N_D and W_N represent the doping concentration and the thickness of the N type layers 160, while N_A and W_P represent the doping concentration and thickness of the P type layers; W_D represents the depletion width; and q represents an electron charge, which cancel out. This device allows for a near ideal rectangular electric field profile at breakdown voltage with sawtooth like ridges. In another exemplary embodiment, the semiconductor power device further includes a sawtooth insulated gate bipolar transistor (IGBT). In another exemplary embodiment, the semiconductor power device further includes a metal oxide semiconductor field effect transistor (MOSFET). In another exemplary embodiment, the semiconductor power device further includes a power diode.

Claims

1. A vertical semiconductor power device formed in a semiconductor substrate comprising:

a first electrode disposed on a top surface and a plurality of dopant regions near the top surface in an epitaxial layer wherein a bottom portion of the epitaxial layer below the dopant regions constituting a uniformly doped region extending continuously and horizontally over an entire length of the semiconductor substrate functioning as a top layer of a drift region and a second electrode disposed on a bottom surface of the semiconductor surface; and

rows of multiple horizontal slices of continuous thin layers of alternating P-type and N-type doped layers disposed immediately below the uniformly doped region of the epitaxial layer extending continuously and horizontally over substantially an entire horizontal length of the semiconductor substrate across the drift region of the semiconductor substrate where each of the continuous thin layers having a doping and a layer thickness to enable a charge balance and a punch through in said alternating doped layers during a conduction mode in conducting a current in a vertical direction between the first electrode and the second electrode perpendicular to and cross over said horizontal slices of said P-doped and N-doped layers.

2. The semiconductor device of claim 1 wherein:

said drift region in said semiconductor substrate for conducting said current through said vertical direction therethrough comprising said horizontal slices of doped layers extending over substantially the entire horizontal length of the semiconductor substrate having a set of said N-type doped layers each disposed next to the said P-type doped layer having a layer thickness of W_P, wherein W_P<

2*W_D*[N_D/(N_A+N_D)] and W_D represents a depletion width, N_D represents a doping concentration of the N-type doped layers, and N_A represents a doping concentration of said P-type doped layers.

3. The semiconductor device of claim 2 wherein:

said drift region in said semiconductor substrate for conducting said current in said vertical direction with said charge balance by having the dopant concentrations and the layer thicknesses satisfying an equation q*N_D*W_N=q*N_A*W_P and q represents an electron charge and W_N represents the layer thicknesses of said continuous N-type doped layers and W_P represents the layer thicknesses of said continuous P-type doped layers.

4. The semiconductor device of claim 1 wherein:

said drift region in said semiconductor substrate having said continuous thin layers of alternating P-type and N-type doped layers extending over substantially the entire horizontal length of the semiconductor substrate conducting said current in said vertical direction while undergoing a punch through from a built in depletion widths of adjacent layers of an alternating conductivity type.

5. The semiconductor device of claim 1 wherein:

said epitaxial layer with said uniformly doped region comprises a uniformly P-doped region disposed immediately above said drift region having said continuous thin layers of the N-conductivity type disposed next to said continuous thin layers of the P-conductivity type conducting said current in said vertical direction while undergoing a punch through in said thin layers of the P-conductivity type from a built in depletion widths of adjacent layers of said N-conductivity type.

6. The semiconductor device of claim 1 wherein:

said epitaxial layer with said uniformly doped region comprises a uniformly N-doped region disposed immediately above said drift region having said continuous thin layers of the P-conductivity type disposed next to said continuous thin layers of the N-conductivity type conducting said current in said vertical direction while undergoing a punch through in said thin layers of the N-conductivity type from a built in depletion widths of adjacent layers of said P-conductivity type.

7. The semiconductor device of claim 1 wherein:

said semiconductor power device further comprising an insulated gate bipolar transistor (IGBT).

8. The semiconductor device of claim 1 wherein:

said semiconductor power device further comprising an insulated gate bipolar transistors (IGBT) supported on a P-type substrate formed with a collector disposed on a bottom surface of said P-type substrate having a N-type drift region supported on said P-type substrate with an emitter disposed on a top surface.

9. The semiconductor device of claim 1 wherein:

said semiconductor power device further comprising a metal oxide semiconductor field effect transistor (MOSFET).

10. The semiconductor device of claim 8 wherein:

said semiconductor power device further comprising an N-channel MOSFET.

11. The semiconductor device of claim 8 wherein:

said semiconductor power device further comprising a P-channel MOSFET.

12. The semiconductor device of claim 1 wherein:

said semiconductor power device further comprising an emitter switching thyristor.

13. The semiconductor device of claim 1 wherein:

said semiconductor power device further comprising a power diode.

14. The semiconductor device of claim 1 wherein:

said semiconductor power device further comprising a power diode supported on a N+ substrate with a N−

drift regions supported thereon having a cathode disposed on a bottom surface of said substrate and an anode dispose on a top surface.

15. A vertical semiconductor power device formed in a semiconductor substrate comprising:

a first electrode disposed on a top surface and a plurality of dopant regions near the top surface in an epitaxial layer wherein a bottom portion of the epitaxial layer below the dopant regions constituting a uniformly doped region extending continuously and horizontally over an entire length of the semiconductor substrate functioning as a top layer of a drift region and a second electrode disposed on a bottom surface of the semiconductor surface; and

rows of multiple horizontal slices of continuous thin layers of alternating P-type and N-type doped layers disposed immediately below the uniformly doped region of the epitaxial layer extending continuously and horizontally under an insulated gate over substantially an entire horizontal length of the semiconductor substrate across the drift region of the semiconductor substrate where each of the continuous thin layers having a doping and a layer thickness to enable a charge balance and a punch through in said alternating doped layers during a conduction mode in conducting a current in a vertical direction between the first electrode and the second electrode perpendicular to and cross over said horizontal slices of said P-doped and N-doped layers.

16. The semiconductor device of claim 15 wherein:

said drift region in said semiconductor substrate for conducting said current through said vertical direction therethrough comprising said horizontal slices of doped layers below the insulated gate having a set of said N-type doped layers each disposed next to the said P-type doped layer having a layer thickness of W_P, wherein W_P<

2*W_D*[N_D/(N_A+N_D)] and W_D represents a depletion width, N_D represents a doping concentration of the N-type doped layers, and N_A represents a doping concentration of said P-type doped layers.

17. The semiconductor device of claim 16 wherein:

said drift region in said semiconductor substrate for conducting said current in said vertical direction with said charge balance by having the dopant concentrations and the layer thicknesses satisfying an equation q*N_D*W_N=q*N_A*W_P and q represents an electron charge and W_N represents the layer thicknesses of said continuous N-type doped layers and W_P represents the layer thicknesses of said continuous P-type doped layers.

18. The semiconductor device of claim 15 wherein:

said drift region in said semiconductor substrate having said continuous thin layers of alternating P-type and N-type doped layers below the insulated gate conducting said current in said vertical direction while undergoing a punch through from a built in depletion widths of adjacent layers of an alternating conductivity type.

19. The semiconductor device of claim 15 wherein:

said semiconductor power device further comprising an insulated gate bipolar transistor (IGBT).

20. The semiconductor device of claim 15 wherein:

said semiconductor power device further comprising a metal oxide semiconductor field effect transistor (MOSFET).