Strained transistor with optimized drive current and method of forming

• US 8,558,278 B2
• Filed: 09/04/2007
• Issued: 10/15/2013
• Est. Priority Date: 01/16/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chuang, Harry, Thei, Kong-Beng, Guo, Wen-Huei, Liang, Mong Song
• Primary Examiner(s): Pizarro, Marcos D.
• Assistant Examiner(s): TANG, SUIAN
• Application Number:
  US11/849,798
• Publication Number:
  US 20080169484A1
• Time in Patent Office: 2,233 Days
• Field of Search: 257/223, 257/227, 257/291, 257/292, 257/439, 257/443, 257/655, 257/E27.1, 257/E27.125, 257/E27.112, 257/E29.117, 257/E29.145, 257/E29.147, 257/E29.151, 257/E29.182, 257/E29.202, 257/E29.273, 257/E29.274, 257/E29.275, 257/E29.276, 257/E29.277, 257/E29.278, 257/E29.279, 257/E29.28, 257/E29.281, 257/E29.282, 257/E29.283, 257/E29.284, 257/E29.285, 257/E29.286, 257/E29.287, 257/E29.288, 257/E29.289, 257/E29.29, 257/E29.291, 257/E29.292, 257/E29.293, 257/E29.294, 257/E29.295, 257/E29.296, 257/E29.297, 257/E29.298, 257/E29.299, 257/E29.314, 257/E29.32, 257/E23.016, 438/149, 438/257
• US Class Current: 257/190
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A strain-induced layer is formed atop a MOS device in order to increase carrier mobility in the channel region. The dimension of the strain-induced layer in preferred embodiments may lead to an optimized drive current increase and improved drive current uniformity in an NMOS and PMOS device. An advantage of the preferred embodiments is that improved device performance is obtained without adding complex processing steps. A further advantage of the preferred embodiments is that the added processing steps can be readily integrated into a known CMOS process flow. Moreover, the creation of the photo masks defining the tensile and compressive strain-induced layers does not require extra design work on an existed design database.

Claims

1. A semiconductor device formed in a substrate comprising:

an active region;

a gate electrode overlying the active region;

a source region and a drain region formed on opposite sides of the gate electrode, the source region and the drain region being substantially aligned with the electrode; and

a strain-induced layer substantially conformally over the gate electrode and the active region;

wherein a first shortest distance between a first gate edge of the gate electrode and a first outermost edge of the strain-induced layer along a direction parallel to a current flow between the source region and the drain region in a plan view is greater than 0.4 um, wherein the strain-induced layer extends a shorter distance from the first gate edge than the active region in the direction parallel to the current flow;

wherein a second shortest distance between a first edge of the active region and a second outermost edge of the strain-induced layer along a direction perpendicular to the current flow between the source region and the drain region in a plan view is between about 60 nm to about 400 nm.

2. The semiconductor device of claim 1 is a PMOS transistor and said strain-induced layer is a compressive-stress layer.

3. The semiconductor device of claim 2 wherein said compressive-stress layer comprises one of SiN (silicon nitride), oxynitride, oxide, SiGe or the combinations of the elements above.

4. The semiconductor device of claim 1 wherein said substrate is one of an N-well formed on a silicon substrate, a bulk silicon substrate, a substrate made of strained semiconductor, compound semiconductor, multi-layers semiconductor, silicon on insulator (SOI), and the like.

5. The semiconductor device of claim 1 wherein said strain-induced layer has a multi-layers configuration.

6. The semiconductor device of claim 1 wherein said strain-induced layer has a thickness from about 5 nm to about 500 nm.

7. The semiconductor device of claim 1 wherein said source region and drain region further comprises a material having a lattice constant different from that of the surrounding substrate material.

8. A semiconductor device formed in a semiconductor substrate comprising:

a first PMOS transistor formed in a P-type active region, the first PMOS transistor comprising a first poly gate electrode overlying the P-type active region;

an first NMOS transistor formed in an N-type active region, the first NMOS transistor comprising a second poly gate electrode overlying said N-type active region; and

a first compressive-stress layer substantially conformally over the first poly gate electrode and the P-type active region;

wherein a first shortest distance in a first direction parallel with a current flow of the first PMOS transistor and between the first poly gate electrode and a first outermost edge of the first compressive-stress layer is greater than 0.4 um, wherein at least a portion of the first outermost edge of the first compressive-stress layer is located over the P-type active region;

wherein a second shortest distance in a second direction perpendicular with the current flow of the first PMOS transistor and between the P-type active region and a second outermost edge of the first compressive-stress layer is in a range of between about 60 nm to about 400 nm.

9. The semiconductor device of claim 8, wherein said first compressive-stress layer comprises one of SiN (silicon nitride), oxynitride, oxide, SiGe or the combinations of the elements above.

10. The semiconductor device of claim 8, wherein the first NMOS transistor further comprises a first tensile-stress layer substantially conformally over the second gate electrode and said N-type active region.

11. The semiconductor device of claim 10, wherein said first tensile-stress layer comprises one of SiN (silicon nitride), oxynitride, oxide, SiC, SiCN, CoSi2 (Co silicide), NiSi2 (Ni silicide), or the combinations of the elements above.

12. The semiconductor device of claim 10, wherein the lateral space between said first tensile-stress layer and said first compressive-stress layer is filled with one of an ILD layer, a dielectric layer having tensile-stress and a dielectric layer having compressive-stress.

13. The semiconductor device of claim 10 further comprises a second PMOS transistor and a second NMOS transistor, covered with a second compressive-stress layer and a second tensile-stress.

14. The semiconductor device of claim 10, wherein said first tensile-stress layer substantially conformally over the portion of the substrate, which is not over with the compressive-stress layer, respectively;

wherein the lateral space between said first and second tensile-stress layers and the lateral space between said first and second compressive-stress layers is filled with one of an ILD layer, a dielectric layer having tensile-stress and a dielectric layer having compressive-stress.

15. The semiconductor device of claim 10, wherein said tensile-stress layer and said compressive-stress layer have a different film thickness.

16. The semiconductor device of claim 10, wherein the first PMOS and the first NMOS transistor further comprise a source and drain region, respectively, wherein said source and drain region comprise an epitaxial layer having a lattice constant different from that of the surrounding substrate material.

17. A PMOS transistor formed in a P-type active region (OD) in a semiconductor substrate comprising:

a gate region overlying the OD region having a poly gate electrode on the top;

a source and drain region formed on the opposite side of the gate region, substantially aligned with an edge of the gate region and the edges of the OD region;

a compressive-stress layer substantially conformally over the gate electrode and the OD region, the compressive-stress layer having a first and second edge, wherein the first edge is an outermost edge of the compressive-stress layer;

wherein the space between an edge of the gate electrode and the first edge of the compressive-stress layer is in the range of one to two times either P or G, whichever is larger, where P is the minimum design rule gate poly to P-type OD dimension, and G is the minimum design rule poly-to-poly spacing on a P-type OD region; and

wherein the space between a P-type OD edge and the second edge of the compressive-stress layer is in the range of between about one-third to about two-thirds of the sum of L and H, where L is the minimum P-type OD to N-well boundary dimension and H is the minimum spacing between an N-type OD and an N-well boundary; and

wherein the compressive-stress layer has at least a portion of the first edge located over the OD region.

18. The PMOS transistor of claim 17 wherein said compressive-stress layer comprises one of SiN (silicon nitride), oxynitride, oxide, SiGe or the combinations of the elements above.

19. The PMOS transistor of claim 17 wherein said source and drain region further comprises a material having a lattice constant different from that of the surrounding substrate material.

20. The PMOS transistor of claim 17 has a rotated orientation such that the opposing edges of said poly gate electrode are not aligned with a horizontal and a vertical direction.