Methods and apparatus for measuring analytes using large scale FET arrays

• US 8,558,288 B2
• Filed: 02/28/2011
• Issued: 10/15/2013
• Est. Priority Date: 12/14/2006
• Status: Active Grant

• Current Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Original Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Inventors: Rothberg, Jonathan M., Hinz, Wolfgang, Johnson, Kim L.
• Primary Examiner(s): Wilson, Allan R
• Assistant Examiner(s): Shamsuzzaman, Mohammed
• Application Number:
  US13/036,710
• Publication Number:
  US 20110230375A1
• Time in Patent Office: 960 Days
• Field of Search: 257/253, 257/414, 438/48, 438/49, 324/71.5, 324/101, 330/104, 330/109, 330/263, 330/9
• US Class Current: 257/253
• CPC Class Codes: C12Q 1/6869 Methods for sequencing
• CPC Class Codes: C12Q 1/6874 involving nucleic acid arrays, e.g. sequencing by hybridisation
• CPC Class Codes: C12Q 2533/101 Primer extension
• CPC Class Codes: C12Q 2565/301 Pyrophosphate (PPi)
• CPC Class Codes: C12Q 2565/607 being a sensor, e.g. electrode
• CPC Class Codes: G01N 27/414 Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
• CPC Class Codes: G01N 27/4145 specially adapted for biomolecules, e.g. gate electrode with immobilised receptors
• CPC Class Codes: G01N 27/4148 Integrated circuits therefor, e.g. fabricated by CMOS processing CMOS processing per se H01L21/82
• CPC Class Codes: H01L 21/306 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/31
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/76155 Jetting means, e.g. ink jet
• CPC Class Codes: H01L 2224/82102 using jetting, e.g. ink jet
• CPC Class Codes: H01L 24/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01052 : Tellurium [Te]
• CPC Class Codes: H01L 2924/01056 : Barium [Ba]
• CPC Class Codes: H01L 2924/01059 : Praseodymium [Pr]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.

Claims

1. A readout circuit for a chemical detector, comprising:

a first operational amplifier coupled to a first bias voltage, the first operational amplifier having a first input and a first output, the first input coupled to a first readout signal line of the chemical detector;

a second operational amplifier coupled to the first bias voltage, the second operational amplifier having a second input and a second output, the second output coupled to a second readout signal line of the chemical detector;

a first transistor having first and second terminals coupled to the first output and second input respectively; and

a current sink coupled to the second input and a second bias voltage;

wherein the first output is coupled to an output signal line.

2. The readout circuit of claim 1, wherein the first transistor is a field effect transistor that includes a gate terminal.

3. The readout circuit of claim 2, wherein the first transistor is diode-connected with the gate terminal coupled to the first terminal of the first transistor.

4. The readout circuit of claim 2, wherein the first field effect transistor has a MOSFET matching error tolerance of an order of approximately ±

1%.

5. The readout circuit of claim 1, wherein the chemical detector includes:

a chemically-sensitive transistor having a first terminal and a second terminal,

said first terminal coupled to the second readout signal line;

a first switch coupling the second terminal of the chemically-sensitive transistor to a current source, said first switch consisting of a second transistor; and

a second switch coupling the second terminal of the chemically-sensitive transistor to the first readout signal line, said second switch consisting of a third transistor;

wherein the first and second switches are controlled by a common selection signal.

6. The readout circuit of claim 5, wherein the first transistor and the chemically sensitive transistor have substantially similar thermal drift characteristics, and thermal drift in the first transistor effectively cancels thermal drift from the chemically-sensitive transistor.

7. The readout circuit of claim 5, wherein the first transistor and chemically-sensitive transistor are both MOSFET transistors.

8. The readout circuit of claim 5, wherein the current source is controlled by a third bias voltage and the current sink is controlled by the second bias voltage, the first and second bias voltages are controlled in tandem to provide a complimentary source and sink current.

9. The readout circuit of claim 1, wherein the chemical detector is a column of chemical detection pixels in an array of chemical detection pixels and each chemical detection pixel of the column is controlled by a row selection signal to generate readout signals to the first and second readout signal lines.