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Integrated decoupling capacitor employing conductive through-substrate vias

  • US 8,558,345 B2
  • Filed: 11/09/2009
  • Issued: 10/15/2013
  • Est. Priority Date: 11/09/2009
  • Status: Active Grant
First Claim
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1. A semiconductor structure comprising a semiconductor chip, wherein said semiconductor chip comprises:

  • a semiconductor substrate having a via present therethrough;

    at least one capacitor present in the via and embedded in said semiconductor substrate; and

    at least one laterally-insulated conductive through-substrate connection structure, wherein each of said at least one capacitor comprises;

    an inner electrode comprising a conductive through-substrate via (TSV) structure;

    a node dielectric present on sidewalls of the via and laterally contacting and laterally enclosing said inner electrode, wherein the node dielectric extends from the via onto a first face and a second face of the semiconductor substrate; and

    an outer electrode laterally contacting and laterally enclosing a portion of said node dielectric, wherein end portions of the outer electrode contact with the node dielectric that is present on the first face and the second face of the semiconductor substrate, wherein a first end of the TSV structure is at the first face of the semiconductor substrate and a second end of the TSV structure is at the second face of the semiconductor substrate so that current can be passed from a semiconductor chip that is in electrical communication to the first end of the TSV structure through the semiconductor substrate to a packing substrate that is in electrical communication with the second end of the TSV structure.

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