Integrated decoupling capacitor employing conductive through-substrate vias

• US 8,558,345 B2
• Filed: 11/09/2009
• Issued: 10/15/2013
• Est. Priority Date: 11/09/2009
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Kim, Tae Hong, Sprogis, Edmund J., McAllister, Michael F., Shapiro, Michael J.
• Primary Examiner(s): Lee, Cheung
• Assistant Examiner(s): JOY, JEREMY J
• Application Number:
  US12/614,883
• Publication Number:
  US 20110108948A1
• Time in Patent Office: 1,436 Days
• Field of Search: 257/532, 257/E29.342, 257/E21.575, 257/301, 257/698, 257/E29.346, 257/E23.057, 257/E21.396, 438386-387
• US Class Current: 257/532
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/1301 Thyristor
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/30105 Capacitance
• CPC Class Codes: H01L 2924/30107 Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A capacitor in a semiconductor substrate employs a conductive through-substrate via (TSV) as an inner electrode and a columnar doped semiconductor region as an outer electrode. The capacitor provides a large decoupling capacitance in a small area, and does not impact circuit density or a Si3D structural design. Additional conductive TSV'"'"'s can be provided in the semiconductor substrate to provide electrical connection for power supplies and signal transmission therethrough. The capacitor has a lower inductance than a conventional array of capacitors having comparable capacitance, thereby enabling reduction of high frequency noise in the power supply system of stacked semiconductor chips.

Claims

1. A semiconductor structure comprising a semiconductor chip, wherein said semiconductor chip comprises:

a semiconductor substrate having a via present therethrough;

at least one capacitor present in the via and embedded in said semiconductor substrate; and

at least one laterally-insulated conductive through-substrate connection structure, wherein each of said at least one capacitor comprises;

an inner electrode comprising a conductive through-substrate via (TSV) structure;

a node dielectric present on sidewalls of the via and laterally contacting and laterally enclosing said inner electrode, wherein the node dielectric extends from the via onto a first face and a second face of the semiconductor substrate; and

an outer electrode laterally contacting and laterally enclosing a portion of said node dielectric, wherein end portions of the outer electrode contact with the node dielectric that is present on the first face and the second face of the semiconductor substrate, wherein a first end of the TSV structure is at the first face of the semiconductor substrate and a second end of the TSV structure is at the second face of the semiconductor substrate so that current can be passed from a semiconductor chip that is in electrical communication to the first end of the TSV structure through the semiconductor substrate to a packing substrate that is in electrical communication with the second end of the TSV structure.

2. The semiconductor structure of claim 1, wherein said inner electrode contiguously extends at least from an upper surface of said semiconductor substrate to a lower surface of said semiconductor substrate, said node dielectric contiguously extends from said upper surface to said lower surface, and said outer electrode comprises a doped semiconductor material.

3. The semiconductor structure of claim 1, wherein each of said at least one laterally-insulated conductive through-substrate connection structure includes:

another conductive TSV structure located in said semiconductor substrate; and

a dielectric tubular structure laterally surrounding said another conductive TSV structure and embedded in said semiconductor substrate.

4. The semiconductor structure of claim 3, further comprising an array of solder balls electrically connecting said semiconductor chip to a mounting structure or another semiconductor chip, wherein first solder balls among said array are electrically connected to said inner electrodes, and second solder balls among said array are electrically connected to conductive TSV structures within said at least one laterally-insulated conductive through-substrate connection structure.

5. A semiconductor structure comprising:

a capacitor located in a via extending through a semiconductor substrate and a contact structure located on said semiconductor substrate, wherein said capacitor comprises;

an inner electrode comprising a conductive through-substrate via (TSV) structure that contiguously extends at least from an upper surface of said semiconductor substrate to a lower surface of said semiconductor substrate;

a node dielectric present on sidewalls of the via that is laterally contacting and laterally enclosing said inner electrode and contiguously extending from said upper surface to said lower surface, wherein the node dielectric extends from the via onto a first face and a second face of the semiconductor substrate; and

an outer electrode laterally contacting and laterally enclosing a portion of said node dielectric, wherein ends of the outer electrode contact the node dielectric that is present on the first face and the second face of the semiconductor substrate, wherein a first end of the conductive TSV structure is at the first face of the semiconductor substrate and a second end of the conductive TSV structure is at the second face of the semiconductor substrate so that current can be passed from a semiconductor chip that is in electrical communication to the first end of the conductive TSV structure through the semiconductor substrate to a packing substrate that is in electrical communication with the second end of the TSV structure, wherein said contact structure is conductively connected to said outer electrode.

6. The semiconductor structure of claim 5, wherein said outer electrode comprises a doped semiconductor material.

7. The semiconductor structure of claim 5, further comprising an laterally-insulated conductive through-substrate connection structure, wherein said laterally-insulated conductive through-substrate connection structure includes:

another conductive TSV structure located in said semiconductor substrate; and

a dielectric tubular structure laterally surrounding said another conductive TSV structure and embedded in said semiconductor substrate.

8. The semiconductor structure of claim 7, wherein said semiconductor substrate comprises a semiconductor material, and said dielectric tubular structure comprises an oxide of said semiconductor material.

9. The semiconductor structure of claim 7, further comprising a dielectric hardmask layer located on one side of said semiconductor substrate, wherein an end surface of said conductive TSV structure, an end surface of said another conductive TSV structure, and an end surface of said contact structure are coplanar with a surface of said hard mask layer.