Alignment for backside illumination sensor

• US 8,558,351 B2
• Filed: 07/16/2012
• Issued: 10/15/2013
• Est. Priority Date: 12/06/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Jen-Cheng, Yaung, Dun-Nian, Wuu, Shou-Gwo
• Primary Examiner(s): POTTER, ROY KARL
• Application Number:
  US13/550,140
• Publication Number:
  US 20120280351A1
• Time in Patent Office: 456 Days
• Field of Search: 257/618, 257/797, 257/E23.179
• US Class Current: 257/618
• CPC Class Codes: H01L 21/71 Manufacture of specific parts of devices defined in group H01L21/70 H01L21/0405, H01L21/0445 , H01L21/28, H01L21/44, H01L21/48 take precedence
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2223/5446 Located in scribe lines
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

Provided is an apparatus that includes an integrated circuit located in a first region of a substrate having first and second opposing major surfaces and an alignment mark located in a second region of the substrate and extending through the substrate between the first and second surfaces.

Claims

1. An apparatus comprising:

a substrate having a first surface opposing a second surface and first and second regions extending between the first and second surfaces, wherein the first region includes an integrated circuit; and

an alignment mark located in the second region of the substrate and including a recess filled with a material, the alignment mark being exposed through at least one of the first and second surfaces of the substrate.

2. The apparatus of claim 1, wherein the material includes at least one of a dielectric material and a conductive material.

3. The apparatus of claim 1, wherein the material includes a dielectric material and a conductive material.

4. The apparatus of claim 1, wherein the material includes silicon dioxide.

5. The apparatus of claim 1, wherein the material includes at least one of tungsten and copper.

6. The apparatus of claim 1, wherein the alignment mark protrudes from one of the first and second surfaces.

7. The apparatus of claim 1, wherein the second region includes a scribe region of the substrate.

8. The apparatus of claim 1, further comprising at least one of a microlens and a color filter disposed over the substrate.

20. The apparatus of claim 1, wherein the material includes a conductive material.

9. An apparatus comprising:

a first substrate coupled to a second substrate, the first substrate including a first region having an integrated circuit and a second region having an alignment mark that includes a recess filled with a material, wherein the material is exposed through a surface of the first substrate.

10. The apparatus of claim 9, wherein the first region includes a shallow trench isolation feature that extends to a first depth within the first substrate, and

wherein the recess of the alignment marks extends to a second depth within the first substrate, the second depth being greater than the first depth.

11. The apparatus of claim 10, wherein the second depth is about two times to about ten times greater than the first depth.

12. The apparatus of claim 10, wherein the shallow trench isolation feature is formed of the material filling the recess of the alignment mark.

13. The apparatus of claim 9, wherein the recess is lined with a dielectric material and wherein the material includes a conductive material.

14. The apparatus of claim 9, wherein the material filling the recess protrudes from the surface of the first substrate.

15. The apparatus of claim 9, wherein the material is coplanar with one of a front surface and a back surface of the first substrate.

16. An apparatus comprising:

a first semiconductor substrate having a first surface and an opposing second surface;

a first recess extending into the first semiconductor substrate to a first depth, wherein the first recess is filled with a material;

a second recess extending into the first semiconductor substrate to a second depth, wherein the second depth is different than the first depth, wherein the second recess is filled with the material;

a second semiconductor substrate coupled to the first semiconductor substrate; and

wherein the material in the first recess is exposed through at least one of the first and second surfaces of the first substrate.

17. The apparatus of claim 16, wherein a top surface of the material in the first recess and a top surface of the material in the second recess are substantially coplanar.

18. The apparatus of claim 16, wherein the first surface is a frontside surface of the first substrate and the second surface is a backside surface of the first substrate, and

wherein the material in the first recess is exposed through the backside surface of the first substrate.

19. The apparatus of claim 18, further comprising an interconnect structure formed over the frontside surface of the first substrate and a pixel array formed over the backside surface of the first substrate.