Methods of making compliant semiconductor chip packages

• US 8,558,386 B2
• Filed: 10/13/2009
• Issued: 10/15/2013
• Est. Priority Date: 10/31/1995
• Status: Expired due to Fees

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Fjelstad, Joseph, Karavakis, Konstantine
• Primary Examiner(s): Graybill, David E
• Application Number:
  US12/587,714
• Publication Number:
  US 20100035382A1
• Time in Patent Office: 1,463 Days
• Field of Search: None
• US Class Current: 257/774
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/02331 Multilayer structure
• CPC Class Codes: H01L 2224/0235 Shape of the redistribution layers
• CPC Class Codes: H01L 2224/0236 Shape of the insulating layers therebetween
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/024 Material of the insulating layers therebetween
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/13008 Bump connector integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48 of an individual wire connector
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/4951 Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 23/498 Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers shape of the substrate H01L23/13
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A method of making a semiconductor chip package is provided in which a compliant layer is provided over a contact bearing face of a semiconductor chip. The compliant layer can have a bottom surface adjacent to the chip face, a top surface facing away from the bottom surface, and at least one sloping surface between the top and bottom surfaces. The compliant layer can be disposed remote in a lateral direction along the contact bearing face from at least one contact adjacent to the sloping surface. Bond ribbons can be formed atop the compliant layer, wherein each bond ribbon electrically connects one of the contacts to an associated conductive terminal at the top surface of the compliant layer. The compliant layer can provide stress relief to the bond ribbons, such as during handling and affixing the assembly to an external substrate. A bond ribbon can include a strip extending along the sloping surface of the compliant layer, the strip having a substantially constant thickness in a direction extending away from the sloping surface.

Claims

1. A method of making a semiconductor chip package comprising:

(a) providing a compliant layer over a first portion of a contact bearing face of a semiconductor chip, said compliant layer having a bottom surface adjacent the contact bearing face, a top surface facing away from the bottom surface, and at least one sloping surface between the top surface and the bottom surface, the compliant layer being spaced apart in a direction along the contact bearing face from at least one contact adjacent to the sloping surface and the compliant layer having a low modulus of elasticity; and

(b) forming bond ribbons of conductive material deposited onto the compliant layer, and onto portions of the semiconductor chip between the compliant layer and the at least one contact, wherein each said bond ribbon electrically connects one of said contacts to an associated conductive terminal at said top surface of said compliant layer, wherein each of at least some of said bond ribbons is electrically connected to a respective contact of said contacts and includes a strip extending along said sloping surface of said compliant layer, said strips being spaced apart from one another on said sloping surface from said bottom surface to said top surface.

2. A method as claimed in claim 1, wherein step (b) includes forming said conductive terminals above said contact bearing face of said semiconductor chip, said compliant layer supporting said conductive terminals above said face.

3. A method as claimed in claim 1, wherein step (b) includes forming said bond ribbons to include first ends electrically connected with said contacts of said semiconductor chip and second ends electrically connected with said conductive terminals.

4. A method as claimed in claim 1, wherein at least a portion of said bond ribbon extends along said contact bearing face away from said compliant layer, wherein said compliant layer is readily compressible so as to permit movement of said strip relative to said portion of said bond ribbon.

5. A method as claimed in claim 4, wherein when performing step (a), said semiconductor chip includes an edge extending away from said contact bearing face and at least some of said contacts are disposed in at least one peripheral region of said contact bearing face adjacent said edge.

6. A method as claimed in claim 1, further comprising (c) forming an encapsulant layer overlying said bond ribbons.

7. A method as claimed in claim 6, wherein said encapsulant layer is selected from the group consisting of a curable liquid, silicone, flexibilized epoxy, thermoplastic and gel.

8. A method as claimed in claim 1, wherein said compliant layer is selected from the group consisting of silicone, flexibilized epoxy, fluoropolymer, thermoplastic polymer and polyimide.

9. A method as claimed in claim 1, further comprising (c) forming a dielectric layer overlying the top surface of said compliant layer and said bond ribbons, wherein said dielectric layer has a plurality of apertures, said terminals being accessible through the apertures.

10. A method as claimed in claim 1, wherein said step (a) includes providing said sloping surface to have a first curved transition region adjoining the top surface of said compliant layer and a second curved transition region adjoining the bottom surface of said compliant layer, the first and second transition regions having respective radii of curvature.

11. A method as claimed in claim 10, wherein said compliant layer is readily compressible in directions transverse to its surfaces and said strip is flexible, such that said compliant layer permits movement of said flexible strip in directions transverse to the first and second transition regions of the at least one sloping surface.

12. A method as claimed in claim 1, wherein step (a) includes providing said compliant layer such that said at least one sloping surface is canted at a non-right angle with respect to said bottom surface.

13. A method as claimed in claim 1, further including, before step (b), depositing a barrier metal atop said contacts.

14. A method as claimed in claim 1, wherein the method is applied to a plurality of undiced semiconductor chips to form a plurality of compliant semiconductor chip packages, the method further comprising separating said packages from one another after step (b).

15. A method as claimed in claim 1, wherein the method is applied to a plurality of adjacent semiconductor chips arranged in an array to form a corresponding plurality of compliant semiconductor chip packages, the method further comprising separating said packages from one another after step (b).

16. A method of making a semiconductor chip package comprising:

(a) providing a compliant layer over a first portion of a contact bearing face of a semiconductor chip such that a second portion of the contact bearing face is not covered by the compliant layer, said compliant layer having a bottom surface adjacent the contact bearing face, a top surface facing away from the bottom surface, and at least one sloping surface between the top surface and the bottom surface, the compliant layer being spaced apart in a direction along the contact bearing face from at least one contact adjacent to the sloping surface and the compliant layer having a low modulus of elasticity; and

(b) forming bond ribbons of conductive material deposited onto at least the compliant layer and the contacts, wherein each said bond ribbon electrically connects one of said contacts to an associated conductive terminal at said top surface of said compliant layer,

wherein each of at least some of said bond ribbons includes a flexible strip portion extending along said sloping surface of said compliant layer, and a second portion extending away from said compliant layer towards one of said contacts, said flexible strip portions being spaced apart from one another on said sloping surface from said bottom surface to said top surface, wherein said compliant layer is readily compressible in directions transverse to its surfaces so as to permit movement of said flexible strip portion relative to said second portion.

17. A method as claimed in claim 16, wherein said at least one bond ribbon includes a third portion extending along said top surface, wherein said compliant layer permits movement of said flexible strip portion relative to said third portion.

18. A method as claimed in claim 16, wherein said step (a) includes providing said sloping surface to have a first curved transition region adjoining the top surface of said compliant layer and a second curved transition region adjoining the bottom surface of said compliant layer, the first and second transition regions having respective radii of curvature, wherein said compliant layer permits movement of said flexible strip portion relative to said second portion at said second transition region.

19. A method as claimed in claim 17, wherein said step (a) includes providing said sloping surface to have a first curved transition region adjoining the top surface of said compliant layer and a second curved transition region adjoining the bottom surface of said compliant layer, the first and second transition regions having respective radii of curvature, wherein said compliant layer permits movement of said flexible strip portion relative to said third portion at said first transition region.

20. A method as claimed in claim 16, further comprising:

before step (a), providing a first dielectric layer over the contact bearing face, the first dielectric layer having a plurality of apertures in substantial alignment with said contacts for providing access to said contacts, wherein step (a) includes providing the compliant layer over said first dielectric layer.

21. A method as claimed in claim 20, wherein step (b) includes electroplating said bond ribbons atop said compliant layer including electroplating said at least one flexible strip portion.

22. A method as claimed in claim 16, wherein step (b) includes forming said bond ribbons to include first ends electrically connected with said contacts of said semiconductor chip and second ends electrically connected with said conductive terminals.

23. A method as claimed in claim 16, wherein said semiconductor chip includes an edge extending away from said contact bearing face, at least some of said contacts being disposed in at least one peripheral region of said face adjacent said edge, and step (a) includes providing said compliant layer such that said at least some contacts are exposed beyond said sloping surface of said compliant layer.

24. A method as claimed in claim 16, further comprising (c) forming an encapsulant layer overlying said bond ribbons.

25. A method as claimed in claim 24, further including the step of providing a second dielectric protective layer atop the encapsulant layer, wherein the second dielectric protective layer has a plurality of apertures for accessing said terminals therethrough.

26. A method as claimed in claim 24, wherein said encapsulant layer is selected from the group consisting of a curable liquid, silicone, flexibilized epoxy, thermoplastic and gel.

27. A method as claimed in claim 16, wherein said compliant layer is selected from the group consisting of silicone, flexibilized epoxy, fluoropolymer, thermoplastic polymer and polyimide.

28. A method as claimed in claim 16, further comprising (c) forming a dielectric layer overlying the top surface of said compliant layer and said bond ribbons, wherein said dielectric layer has a plurality of apertures, said terminals being accessible through the apertures.

29. A method as claimed in claim 16, further including, before step (b), depositing a barrier metal atop said contacts.

30. A method as claimed in claim 16, wherein the method is applied to a plurality of undiced semiconductor chips to form a plurality of compliant semiconductor chip packages, the method further comprising separating said packages from one another after step (b).

31. A method as claimed in claim 16, wherein the method is applied to a plurality of adjacent semiconductor chips arranged in an array to form a corresponding plurality of compliant semiconductor chip packages, the method further comprising separating said packages from one another after step (b).