Bus driver for avoiding an overvoltage

• US 8,558,520 B2
• Filed: 09/30/2008
• Issued: 10/15/2013
• Est. Priority Date: 09/30/2008
• Status: Active Grant

• Current Assignee: VLSI Technology LLC (FIG LLC (d/b/a Fortress Investment Group LLC))
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Huot-Marchand, Alexis, Ahmed, Hamada, Besse, Patrice, Jarrige, Nicolas
• Primary Examiner(s): Berhane, Adolf
• Assistant Examiner(s): NASH, GARY A
• Application Number:
  US13/120,874
• Publication Number:
  US 20110175592A1
• Time in Patent Office: 1,841 Days
• Field of Search: 323223-226, 323/269, 323/272, 323/289, 361/91.1, 361/91.3, 361/93.1, 363/56.11
• US Class Current: 323/269
• CPC Class Codes: H03K 17/0822 in field-effect transistor switches
• CPC Class Codes: H03K 17/167 using parallel switching arrangements
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits

Abstract

An electrical circuit for manipulating at least one of a voltage and a current on a bus wire comprises a first switch having a first gate, a first source, and a first potential reduction unit. The first potential reduction unit is suitable for lowering a potential difference between the first gate and the first source of the first switch, wherein the lowering of the potential difference is caused by a shutting-off of a first control voltage.

Claims

1. An electrical circuit for manipulating at least one of a voltage and a current on a bus wire, wherein the circuit comprises:

a first switch having a first gate, a first source, and a first potential reduction unit, wherein the manipulating of the at least one of a voltage and a current on the bus wire is controllable by a change of a gate voltage at the first gate, wherein the first potential reduction unit is suitable for lowering a potential difference between the first gate and the first source of the first switch, wherein the lowering of the potential difference is causable by turning an output of a first control voltage source into an high-impedance state; and

a second switch having a second gate, a second source, and a second potential reduction unit, wherein the second potential reduction unit is suitable for lowering a potential difference between the second gate and the second source of the second switch, wherein the lowering of the potential difference is caused by a shutting-off of a second control voltage.

2. The electrical circuit as claimed in claim 1, wherein the second potential reduction unit has a higher time constant than the first potential reduction unit.

3. The electrical circuit as claimed in claim 2, wherein the second potential reduction unit comprises the first potential reduction unit.

4. The electrical circuit as claimed in claim 2, wherein a resistor of the second potential reduction unit is connected in series with the first potential reduction unit.

5. The electrical circuit as claimed in claim 2, wherein at least one of the first potential reduction unit and the second potential reduction unit forms at least a portion of respective first and second timing elements.

6. The electrical circuit as claimed in claim 2, wherein at least one of the first and second potential reduction unit forms at least a portion of a first respectively second timing element.

7. The electrical circuit as claimed in claim 1, wherein the second potential reduction unit comprises the first potential reduction unit.

8. The electrical circuit as claimed in claim 7, wherein a resistor of the second potential reduction unit is connected in series with the first potential reduction unit.

9. The electrical circuit as claimed in claim 7, wherein at least one of the first and second potential reduction unit forms at least a portion of a first respectively second timing element.

10. The electrical circuit as claimed in claim 1, wherein a resistor of the second potential reduction unit is connected in series with the first potential reduction unit.

11. The electrical circuit as claimed in claim 1, wherein at least one of the first potential reduction unit and the second potential reduction unit forms at least a portion of respective first and second timing elements.

12. The electrical circuit as claimed in claim 11, wherein at least one of the first and second timing elements comprises a first respectively second capacity.

13. The electrical circuit as claimed in claim 12, wherein at least one of the first and second timing elements comprises a first respectively second RC element.

14. The electrical circuit as claimed in claim 13, wherein at least one of the first and second timing elements comprises a first respectively second current source.

15. The electrical circuit as claimed in claim 12, wherein at least one of the first and second timing elements comprises a first respectively second current source.

16. The electrical circuit as claimed in claim 11, wherein at least one of the first and second timing elements comprises a first respectively second current source.

17. The electrical circuit of claim 1, wherein the first switch is an NMOS transistor.

18. A method for avoiding an overvoltage on a bus wire, wherein the method comprises:

recognizing an error condition;

breaking a first control circuit of a first gate of a first switch at an interruption moment when the first gate is supplied via the first control circuit with a first control voltage by turning an output of a first control voltage source into an high impedance state;

lowering a voltage at the first gate with a first time constant;

breaking a second control circuit of a second gate of a second switch, at the interruption moment when the second gate is supplied via the second control circuit with a second control voltage; and

lowering a voltage at the second gate with a second time constant being higher than the first time constant.

19. The method of claim 18, wherein the first switch is an NMOS transistor.

20. An electrical circuit for manipulating at least one of a voltage and a current on a bus wire, wherein the electrical circuit comprises:

a voltage supply having a first terminal coupled to the bus wire, and a second terminal coupled to a voltage reference, wherein the voltage reference is a ground;

a protection circuit having a first terminal coupled to the bus wire, and a second terminal coupled to the voltage reference;

a switch having a first current electrode coupled to the bus wire, a second current electrode coupled to the voltage reference, and a control electrode; and

a potential reduction unit including a gate-source capacitor of the switch, and a resistor having a first terminal coupled to the control electrode of the switch and a second terminal coupled to the voltage reference, wherein the manipulating of the at least one of the voltage and the current on the bus wire is controllable by a change of a control voltage at the control electrode of the switch, wherein the potential reduction unit is suitable for lowering a potential difference between the control electrode and the second current electrode of the switch, wherein the lowering of the potential difference is causable by turning an output of a first control voltage source into an high-impedance state.