System and method for bootstrapping a switch driver

• US 8,558,584 B2
• Filed: 11/30/2010
• Issued: 10/15/2013
• Est. Priority Date: 11/30/2010
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Draxelmayr, Dieter, Norling, Karl
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): CHENG, DIANA
• Application Number:
  US12/956,813
• Publication Number:
  US 20120133420A1
• Time in Patent Office: 1,050 Days
• Field of Search: 327108-112, 327387-391, 327588-589, 326 26- 27, 326/82, 326/83, 326/86, 326/89, 326/90, 326/92
• US Class Current: 327/108
• CPC Class Codes: H02M 3/33571 Half-bridge at primary side of an isolation transformer
• CPC Class Codes: H02M 3/33573 Full-bridge at primary side of an isolation transformer
• CPC Class Codes: H02M 7/538 in a push-pull configuration H02M7/5375 takes precedence ; with oscillating arrangements H02M7/53832, H02M7/53846
• CPC Class Codes: H03K 17/94 characterised by the way in which the control signals are generated
• CPC Class Codes: H03K 2017/6875 using self-conductive, depletion FETs
• CPC Class Codes: H03K 2217/0081 Power supply means, e.g. to the switch driver
• CPC Class Codes: H03K 5/1515 non-overlapping

Abstract

In accordance with an embodiment, a driver circuit includes a low-side driver having a first output configured to be coupled to a control node of a first semiconductor switch, and a reference input configured to be coupled to a reference node of the first semiconductor switch. The low-side driver also includes a first capacitor coupled between an output node of the first semiconductor switch and a first node, a first diode coupled between the first node and a first power input of the driver, and a second capacitor coupled between the first power input of the low-side driver and the reference node of the first semiconductor switch.

Claims

1. A driver circuit comprising:

a low-side driver comprising a first output configured to be coupled to a control node of a first semiconductor switch, and a reference input configured to be coupled to a reference node of the first semiconductor switch, wherein the first semiconductor switch comprises a normally-on device in series with a switch transistor, and the normally-on device conducts electricity when a voltage between the control node and the reference node is about zero volts;

a first capacitor coupled between an output node of the first semiconductor switch and a first node;

a first diode coupled between the first node and a first power input of the driver; and

a second capacitor coupled between the first power input of the low-side driver and the reference node of the first semiconductor switch.

2. The driver circuit of claim 1, further comprising:

a high-side driver comprising a first output configured to be coupled to a control node of a second semiconductor switch, and a reference input configured to be coupled to an output node of the second semiconductor switch, wherein the output node of the second semiconductor switch is coupled to the output node of the first semiconductor switch;

a third capacitor coupled between a first power input of the high-side driver and the reference input of the high side driver;

a second diode coupled between a high-side reference potential node and the first power input of the high-side driver; and

a third diode coupled between the first node and the high-side reference potential node.

3. The driver of claim 2, wherein the high-side driver and the low-side driver provide drive signals for an half-bridge circuit, the half-bridge circuit comprising the first semiconductor switch and the second semiconductor switch.

4. The driver of claim 2, further comprising a power supply coupled between a reference node of the second semiconductor switch and the high-side reference potential node.

5. The driver of claim 1, wherein the normally-on device comprises a JFET and the switch transistor comprises a MOSFET.

6. A driver circuit comprising:

a low-side driver comprising a first output configured to be coupled to a control node of a first semiconductor switch, and a reference input configured to be coupled to a reference node of the first semiconductor switch, wherein

the first semiconductor switch comprises a normally-on device in series with a switch transistor, and

the normally-on device comprises a JFET and the switch transistor comprises a MOSFET;

a first capacitor coupled between an output node of the first semiconductor switch and a first node;

a first diode coupled between the first node and a first power input of the driver; and

a second capacitor coupled between the first power input of the low-side driver and the reference node of the first semiconductor switch.

7. The driver of claim 6, wherein the MOSFET comprises a PMOS device.

8. The driver of claim 6, wherein the low-side driver:

keeps the MOSFET off when a reference supply voltage is below a first threshold voltage;

operates the MOSFET and the JFET together when the reference supply voltage is between the first threshold voltage and a second threshold voltage; and

keeps the MOSFET on when the reference supply voltage is greater than the second threshold voltage.

9. The driver of claim 8, wherein the reference supply voltage is comprises a voltage proportional to a voltage of the first power input of the low side driver.

10. The driver of claim 8, wherein the low-side driver comprises a voltage regulator coupled between the first power input of the low-side driver, wherein:

the voltage regulator comprises an output; and

the reference supply voltage comprises a voltage proportional to a voltage of the output of the voltage regulator.

11. The driver of claim 8, wherein the low-side driver operates the MOSFET and the JFET together by turning on the MOSFET before turning on the JFET, and turning off the JFET before turning off the MOSFET.

12. A method of operating a switch driver comprising a low-side driver coupled to a first switch, the method comprising:

charging a supply node of the low-side driver with a first network coupled between an output of a first switch and a supply node of the low-side driver, the first network comprising a capacitor in series with a first diode, wherein the first switch comprises a normally-on device in series with a switch transistor, and the normally-on device conducts electricity when a voltage between a control node of the normally-on device and a reference node of the normally-on device is about zero volts.

13. The method of claim 12, wherein charging the supply node comprises charging the supply node below ground potential.

14. The method of claim 12, wherein:

the switch driver further comprises a high-side driver coupled to a second switch, the second switch coupled in series with the first switch; and

the method further comprises charging a supply node of the high-side driver with a second network coupled between an output of the second switch and supply node of the high side driver, the second network comprising the capacitor in series with a second diode.

15. The method of claim 12, wherein:

the first switch comprises a JFET device in series with a MOSFET device; and

the method further comprises;

operating the JFET device and the MOSFET device together when supply nodes of the switch driver are charging up after the switch driver has started up; and

keeping the MOSFET device on while turning the JFET device on and off after the supply nodes of the switch driver are charged to a full operating state.

16. The method of claim 15, further comprising keeping the MOSFET device off during startup of the switch driver.

17. The method of claim 12, wherein:

the first switch comprises a JFET device in series with a MOSFET device; and

the method further comprises;

operating the JFET device and the MOSFET device together when a reference supply voltage is between a first threshold voltage and a second threshold voltage; and

keeping the MOSFET device on while turning the JFET device on and off when the reference supply voltage is greater than the second threshold voltage.

18. The method of claim 17, further comprising keeping the MOSFET device off when the reference supply voltage is below the first threshold voltage.

19. The method of claim 17, wherein operating the JFET device and the MOSFET device together comprises:

turning on the MOSFET device before turning on the JFET device; and

turning off the JFET device before turning off the MOSFET device.

20. The method of claim 12, wherein:

the method further comprises;

operating the normally-on device and the switch transistor together when supply nodes of the switch driver are charging up after the switch driver has started up; and

keeping the switch transistor on while turning the normally-on device on and off after the supply nodes of the switch driver are charged to a full operating state.

21. A system comprising:

a first switch coupled in series with a second switch at a common node;

a low-side driver coupled to the first switch;

a high-side driver coupled to the second switch;

a bootstrap capacitor having a first end coupled to the common node;

a first diode coupled between a second end of the bootstrap capacitor and power supply node of the low-side driver;

a first storage capacitor coupled between the power supply node of the low-side driver and a reference node of the low-side driver;

a second diode coupled between the second end of the bootstrap capacitor and a power supply node of the high-side driver; and

a second storage capacitor coupled between the power supply node of the high-side driver and a reference node of the high-side driver.

22. The system of claim 21, wherein

the first switch comprises a first JFET in series with a first MOSFET;

the second switch comprises a second JFET in series with a second MOSFET;

the low-side driver is configured to;

keep the first MOSFET off when a first reference supply voltage is below a first threshold voltage;

operate the first MOSFET and the first JFET together when the first reference supply voltage is between the first threshold voltage and a second threshold voltage; and

keep the first MOSFET on and operate the first JFET when the first reference supply voltage is greater than the second threshold voltage; and

the high-side driver is configured to;

keep the second MOSFET off when a second reference supply voltage is below a third threshold voltage;

operate the second MOSFET and the second JFET together when the second reference supply voltage is between the third threshold voltage and a fourth threshold voltage; and

keep the second MOSFET on and operate the second JFET when the second reference supply voltage is greater than the fourth threshold voltage.

23. The system of claim 22, wherein:

the low-side driver is configured to operate the first MOSFET and the first JFET together by turning on the first MOSFET before turning on the first JFET, and turning off the first JFET before turning off the first MOSFET; and

the high-side driver is configured to operate the second MOSFET and the second JFET together by turning on the second MOSFET before turning on the second JFET, and turning off the second JFET before turning off the second MOSFET.

24. The system of claim 22, further comprising:

a transformer coupled to the common node; and

a power supply controller coupled to the low-side driver and the high-side driver, wherein the power supply is configured to regulate a voltage of a power supply output node coupled to the transformer.

25. The system of claim 21, wherein

the first switch comprises a first normally-on device in series with a first switch transistor;

the second switch comprises a second normally-on device in series with a second switch transistor;

the low-side driver is configured to;

keep the first switch transistor off when a first reference supply voltage is below a first threshold voltage;

operate the first switch transistor and the first normally-on device together when the first reference supply voltage is between the first threshold voltage and a second threshold voltage; and

keep the first switch transistor on and operate the first normally-on device when the first reference supply voltage is greater than the second threshold voltage; and

the high-side driver is configured to;

keep the second switch transistor off when a second reference supply voltage is below a third threshold voltage;

operate the second switch transistor and the second normally-on device together when the second reference supply voltage is between the third threshold voltage and a fourth threshold voltage; and

keep the second switch transistor on and operate the second normally-on device when the second reference supply voltage is greater than the fourth threshold voltage.

26. The system of claim 21, wherein:

the first switch comprises a first normally-on device in series with a first switch transistor;

the second switch comprises a second normally-on device in series with a second switch transistor;

the low-side driver is configured to;

keep the first switch transistor off when a first reference supply voltage is below a first threshold voltage;

operate the first switch transistor and the first normally-on device together when the first reference supply voltage is between the first threshold voltage and a second threshold voltage; and

keep the first switch transistor on and operate the first normally-on device when the first reference supply voltage is greater than the second threshold voltage; and

the high-side driver is configured to;

keep the second switch transistor off when a second reference supply voltage is below a third threshold voltage;

operate the second switch transistor and the second normally-on device together when the second reference supply voltage is between the third threshold voltage and a fourth threshold voltage; and

keep the second switch transistor on and operate the second normally-on device when the second reference supply voltage is greater than the fourth threshold voltage.

27. A driver circuit comprising:

a low-side driver comprising a first output configured to be coupled to a control node of a first semiconductor switch, and a reference input configured to be coupled to a reference node of the first semiconductor switch;

a first capacitor coupled between a first power input of the low-side driver and the reference node of the first semiconductor switch;

a high-side driver comprising a first output configured to be coupled to a control node of a second semiconductor switch, and a reference input configured to be coupled to an output node of the second semiconductor switch, wherein the output node of the second semiconductor switch is coupled to the output node of the first semiconductor switch;

a second capacitor coupled between a first power input of the high-side driver and the reference input of the high side driver;

a first diode coupled between a high-side reference potential node and the first power input of the high-side driver; and

a second diode coupled between the first power input of the high-side driver and the first power input of the low-side driver.

28. The driver of claim 27, further comprising a power supply coupled between a reference node of the second semiconductor switch and the high-side reference potential node.