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Repetitive single cycle pulse width modulation generation

  • US 8,558,632 B2
  • Filed: 09/29/2011
  • Issued: 10/15/2013
  • Est. Priority Date: 09/29/2011
  • Status: Active Grant
First Claim
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1. An apparatus for generating a repetitive single cycle PWM signal, comprising:

  • a duty cycle register storing a duty cycle value;

    a duty cycle counter having a clock input coupled to a clock generating a plurality of clock pulses and incrementing a duty cycle count value for each of the plurality of clock pulses received;

    a duty cycle comparator coupled to the duty cycle register and the duty cycle counter, wherein the duty cycle comparator compares the duty cycle count value to the duty cycle value and generates a PWM signal when the duty cycle count value is less than or equal to the duty cycle value and stops the duty cycle counter when the duty cycle count value is greater than the duty cycle value;

    a phase counter having a clock input coupled to the clock generating the plurality of clock pulses and incrementing a phase count value for each of the plurality of clock pulses received, and a reset input adapted for coupling to a PWM cycle start signal from a time base, wherein when the PWM cycle start signal is asserted the phase count value is reset to zero, thereby restarting the phase counter;

    a phase offset register storing a phase offset value; and

    a phase offset comparator coupled to the phase offset register, the phase counter and a stop input thereof, wherein the phase offset comparator compares the phase count value to the phase offset value and stops the phase counter when the phase count value is equal to the phase offset value and resets the duty cycle value to zero, thereby restarting the duty cycle counter.

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