Vialess integration for dual thin films—thin film resistor and heater

• US 8,558,654 B2
• Filed: 12/29/2011
• Issued: 10/15/2013
• Est. Priority Date: 09/17/2008
• Status: Expired due to Fees

• Current Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Original Assignee: Stmicroelectronics Pte Limited (STMicroelectronics NV), STMicroelectronics SAS (STMicroelectronics NV), STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Le Neel, Olivier, Privitera, Stefania Maria Serena, Leung, Calvin, Dumont-Girard, Pascale, Castorina, MaurizoGabriele
• Primary Examiner(s): LEE, KYUNG S
• Application Number:
  US13/340,255
• Publication Number:
  US 20120112873A1
• Time in Patent Office: 656 Days
• Field of Search: 338/22.R, 338/22.SD, 338/25
• US Class Current: 338/22.R
• CPC Class Codes: H01C 17/0656 composed of silicides H01C17/0652 takes precedence
• CPC Class Codes: H01C 17/265 by chemical or thermal treatment, e.g. oxydation, reduction, annealing etching H01C17/2416
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 23/345 Arrangements for heating thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/016 Thin-film circuits
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/1301 Thyristor
• CPC Class Codes: H01L 2924/13033 TRIAC - Triode for Alternating Current - A bidirectional switching device containing two thyristor structures with common gate contact
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

A process is described for integrating two closely spaced thin films without deposition of the films through deep vias. The films may be integrated on a wafer and patterned to form a microscale heat-trimmable resistor. A thin-film heating element may be formed proximal to a thin-film resistive element, and heat generated by the thin-film heater can be used to permanently trim a resistance value of the thin-film resistive element. Deposition of the thin films over steep or abrupt topography is minimized by using a process in which the thin films are deposited in a sequence that falls between depositions of thick metal contacts to the thin films.

Claims

1. A heat-trimmable thin-film resistor comprising:

a thin-film resistive element configured as a resistor that is electrically connected to a first conductive interconnect formed at a first level located in the direction of a first facing side of the thin-film resistive element;

a thin-film heating element proximal at least a portion of the thin-film resistive element, wherein a first facing side of the thin-film heating element is located proximal a second facing side of the thin-film resistive element; and

a second conductive interconnect formed at a second facing side of the thin-film heating element.

2. The heat-trimmable resistor of claim 1, wherein the first conductive interconnect is formed prior to the formation of the thin-film resistive element.

3. The heat-trimmable resistor of claim 1, wherein the second conductive interconnect is formed after formation of the thin-film heating element.

4. The heat-trimmable resistor of claim 3, wherein a portion of the second conductive interconnect covers substantially all of at least one non-active region of the heat-trimmable resistor.

5. The heat-trimmable resistor of claim 1, further comprising a thermally conductive layer located between the first facing side of the thin-film heating element and second facing side of the thin-film resistive element.

6. The heat-trimmable resistor of claim 5, wherein the thermally conductive layer comprises Si₃N₄ or SiC.

7. The heat-trimmable resistor of claim 5, wherein the thickness of the thermally conductive layer is between about 50 nm and about 400 nm.

8. The heat-trimmable resistor of claim 1, wherein the thin-film heating element is patterned to include a plurality of elongate legs.

9. The heat-trimmable resistor of claim 8, wherein the elongate legs have lengths between about 10 microns and about 300 microns and widths between about 250 nm and about 10 microns and thicknesses between about 5 nm and about 100 nm.

10. The heat-trimmable resistor of claim 1, wherein the thin-film heating element comprises TaAl.

11. The heat-trimmable resistor of claim 1, wherein the thin-film resistive element comprises CrSi.

12. The heat-trimmable resistor of claim 11, wherein the thickness of the thin-film resistive element is between about 3 nm and about 20 nm.

13. The heat-trimmable resistor of claim 1, further comprising at least one contact pad for an external probe, the at least one contact pad electrically connected to the thin-film resistive element or the thin-film heating element.

14. The heat-trimmable resistor of claim 1 incorporated in an integrated circuit.

15. A process for forming an integrated heat-trimmable resistor comprising:

depositing on a substrate a thin-film heating material proximal a thin-film resistive element, wherein the thin-film resistive element connects to a conductive interconnect formed on a side of the thin-film resistive element that is opposite a side facing the thin-film heating material;

patterning the thin-film heating material to form a thin-film heating element; and

depositing, after the depositing of the thin-film heating material, a first conductive interconnect material to be electrically connected to the thin-film heating element.

16. The process of claim 15, further comprising:

depositing on the substrate a thin-film resistive material to be electrically connected to a second conductive interconnect;

patterning the thin-film resistive material to form the thin-film resistive element.

17. The process of claim 15, wherein a portion of the first conductive interconnect covers substantially all of at least one non-active region of the heat-trimmable resistor.

18. The process of claim 15, further comprising depositing a layer of thermally conductive material prior to deposition of the thin-film heating material.

19. The process of claim 18, wherein the thermally conductive material is disposed between the thin-film resistive element and the thin-film heating material.

20. The process of claim 18, wherein the thermally conductive material comprises Si₃N₄ or SiC.

21. The process of claim 18, wherein the thermally conductive material has a thickness between about 50 nm and about 400 nm.

22. The process of claim 15, wherein the thin-film heating material comprises TaAl.

23. The process of claim 15, wherein the thickness of the thin-film heating material is between about 10 nm and about 100 nm.

24. The process of claim 15, wherein the patterning of the thin-film heating material comprises forming elongate heating members in the thin-film heating element.

25. The process of claim 15, further comprising patterning the first conductive interconnect material.

26. The process of claim 25, wherein the patterned first conductive interconnect material forms at least one heater connector extending across non-active regions of the heater.

27. The process of claim 15, wherein the first conductive material comprises AlSiCu.

28. A process for forming electrical contacts to two integrated thin-film layers comprising:

depositing on a substrate a first thin-film layer to be electrically connected to an underlying conductive interconnect;

depositing proximal the first thin-film layer a second thin-film layer to be electrically connected to a second conductive interconnect; and

depositing on the substrate subsequent the deposition of the second thin-film layer the second conductive interconnect.

29. The process of claim 28, wherein the first thin-film layer is separated from the second thin-film layer by a distance between about 50 nm and about 400 nm.

30. The process of claim 28, further comprising patterning the first thin film layer to form a thin-film resistive element or thin-film heating element.

31. The process of claim 28, further comprising patterning the second thin film layer to form a thin-film resistive element or thin-film heating element.

32. A dual thin-film device comprising:

a first thin-film element electrically connected to a first conductive interconnect that is located in a direction of a first facing side of the first thin-film element; and

a second thin-film element having a first facing side that is proximal a second facing side of the first thin-film element and is electrically connected to a second conductive interconnect that is located in a direction of a second facing side of the second thin-film element.

33. The dual thin-film device of claim 32, wherein the first thin-film element comprises a thin-film resistive element.

34. The dual thin-film device of claim 32, wherein the second thin-film element comprises a thin-film heating element.

35. The dual thin-film device of claim 32, wherein the first thin-film element is separated from the second thin-film element by a distance between about 50 nm and about 400 nm.