Semiconductor device
First Claim
Patent Images
1. A semiconductor device comprising:
- a source line;
a bit line;
a first signal line;
a plurality of second signal lines;
a plurality of word lines;
a plurality of memory cells connected in series between the source line and the bit line;
a driver circuit configured to drive the plurality of second signal lines and the plurality of word lines so as to select a memory cell specified by an address signal;
a writing circuit configured to output a writing potential to the first signal line;
a reading circuit configured to compare a plurality of reading potentials and a bit line potential input from the bit line connected to the specified memory cell;
a control circuit configured to select any of a plurality of compensation voltages in response to a comparison result of the bit line potential and the plurality of reading potentials; and
a potential generation circuit configured to generate the writing potential and the plurality of reading potentials to be supplied to the writing circuit and the reading circuit,wherein one of the plurality of memory cells comprises;
a first transistor having a first gate electrode, a first source electrode, and a first drain electrode;
a second transistor having a second gate electrode, a second source electrode, and a second drain electrode; and
a capacitor,wherein a substrate including a semiconductor material is provided with the first transistor,wherein the second transistor includes an oxide semiconductor layer, andwherein the first gate electrode, one of the second source electrode and the second drain electrode, and one of electrodes of the capacitor are electrically connected to each other,wherein the source line and the first source electrode are electrically connected to each other,wherein the bit line and the first drain electrode are electrically connected to each other,wherein the first signal line and the other of the second source electrode and the second drain electrode are electrically connected to each other,wherein one of the plurality of second signal lines and the second gate electrode are electrically connected to each other,wherein one of the plurality of word lines and the other of the electrodes of the capacitor are electrically connected to each other, andwherein the oxide semiconductor layer is formed using an In—
Ga—
Zn—
O-based oxide semiconductor material.
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Accused Products
Abstract
The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is formed on or in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.
153 Citations
18 Claims
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1. A semiconductor device comprising:
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a source line; a bit line; a first signal line; a plurality of second signal lines; a plurality of word lines; a plurality of memory cells connected in series between the source line and the bit line; a driver circuit configured to drive the plurality of second signal lines and the plurality of word lines so as to select a memory cell specified by an address signal; a writing circuit configured to output a writing potential to the first signal line; a reading circuit configured to compare a plurality of reading potentials and a bit line potential input from the bit line connected to the specified memory cell; a control circuit configured to select any of a plurality of compensation voltages in response to a comparison result of the bit line potential and the plurality of reading potentials; and a potential generation circuit configured to generate the writing potential and the plurality of reading potentials to be supplied to the writing circuit and the reading circuit, wherein one of the plurality of memory cells comprises; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; a second transistor having a second gate electrode, a second source electrode, and a second drain electrode; and a capacitor, wherein a substrate including a semiconductor material is provided with the first transistor, wherein the second transistor includes an oxide semiconductor layer, and wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one of electrodes of the capacitor are electrically connected to each other, wherein the source line and the first source electrode are electrically connected to each other, wherein the bit line and the first drain electrode are electrically connected to each other, wherein the first signal line and the other of the second source electrode and the second drain electrode are electrically connected to each other, wherein one of the plurality of second signal lines and the second gate electrode are electrically connected to each other, wherein one of the plurality of word lines and the other of the electrodes of the capacitor are electrically connected to each other, and wherein the oxide semiconductor layer is formed using an In—
Ga—
Zn—
O-based oxide semiconductor material. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10)
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2. A semiconductor device comprising:
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a source line; a bit line; a first signal line; a plurality of second signal lines; a plurality of word lines; a plurality of memory cells connected in series between the source line and the bit line; a driver circuit configured to drive the plurality of second signal lines and the plurality of word lines so as to select a memory cell specified by an inputted address signal; a writing circuit configured to output a first writing potential to the first signal line in a first writing operation, and output any of a plurality of second writing potentials to the first signal line in a second writing operation; a reading circuit configured to read data of the specified memory cell by comparing a first bit line potential input from the bit line connected to the specified memory cell and a plurality of first reading potentials in a first reading operation, and comparing a second bit line potential input from the bit line connected to the specified memory cell and a plurality of second reading potentials in a second reading operation; a control circuit configured to select any of a plurality of compensation voltages in response to a comparison result of the first bit line potential and the plurality of first reading potentials, and select any of the plurality of second writing potentials; and a potential generation circuit configured to generate the first writing potential, the plurality of second writing potentials, the plurality of first reading potentials, and the plurality of second reading potentials to be supplied to the writing circuit and the reading circuit, wherein one of the plurality of memory cells comprises; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; a second transistor having a second gate electrode, a second source electrode, and a second drain electrode; and a capacitor, wherein a substrate including a semiconductor material is provided with the first transistor, wherein the second transistor includes an oxide semiconductor layer, and wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one of electrodes of the capacitor are electrically connected to each other, wherein the source line and the first source electrode are electrically connected to each other, wherein the bit line and the first drain electrode are electrically connected to each other, wherein the first signal line and the other of the second source electrode and the second drain electrode are electrically connected to each other, wherein one of the plurality of second signal lines and the second gate electrode are electrically connected to each other, wherein one of the plurality of word lines and the other of the electrodes of the capacitor are electrically connected to each other, and wherein the oxide semiconductor layer is formed using an In—
Ga—
Zn—
O-based oxide semiconductor material.
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11. A semiconductor device comprising:
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a source line; a bit line; a first memory cell and a second memory cell connected in series between the source line and the bit line; a first signal line electrically connected to the first memory cell and the second memory cell; two second signal lines, one of the two second signal lines electrically connected to the first memory cell, the other of the two second signal lines electrically connected to the second memory cell; two word lines, one of the two word lines electrically connected to the first memory cell, the other of the two word lines electrically connected to the second memory cell; a driver circuit electrically connected to the two second signal lines and the two word lines, and configured to select a memory cell specified by an inputted address signal; a writing circuit configured to output a writing potential to the first signal line; a reading circuit configured to compare a plurality of reading potentials and a bit line potential input from the bit line connected to the specified memory cell; a control circuit configured to select any of a plurality of compensation voltages in response to a comparison result of the bit line potential and the plurality of reading potentials; and a potential generation circuit configured to generate the writing potential and the plurality of reading potentials to be supplied to the writing circuit and the reading circuit, wherein each of the first memory cell and the second memory cell comprises at least one transistor comprising an oxide semiconductor layer, and wherein the oxide semiconductor layer is formed using an In—
Ga—
Zn—
O-based oxide semiconductor material.
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12. A semiconductor device comprising:
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a source line; a bit line; a first memory cell and a second memory cell connected in series between the source line and the bit line; a first signal line electrically connected to the first memory cell and the second memory cell; two second signal lines, one of the two second signal lines electrically connected to the first memory cell, the other of the two second signal lines electrically connected to the second memory cell; two word lines, one of two the word lines electrically connected to the first memory cell, the other of the two word lines electrically connected to the second memory cell; a driver circuit electrically connected to the two second signal lines and the two word lines, and configured to select the first memory cell or the second memory cell specified by an inputted address signal; a writing circuit configured to output a first writing potential to the first signal line in a first writing operation, and output any of a plurality of second writing potentials to the first signal line in a second writing operation; a reading circuit configured to read data of the specified memory cell by comparing a first bit line potential input from the bit line connected to the specified memory cell and a plurality of first reading potentials in a first reading operation, and comparing a second bit line potential input from the bit line connected to the specified memory cell and a plurality of second reading potentials in a second reading operation; a control circuit configured to select any of a plurality of compensation voltages in response to a comparison result of the first bit line potential and the plurality of first reading potentials, and select any of the plurality of second writing potentials; and a potential generation circuit configured to generate the first writing potential, the plurality of second writing potentials, the plurality of first reading potentials, and the plurality of second reading potentials to be supplied to the writing circuit and the reading circuit, wherein each of the first memory cell and the second memory cell comprises a first transistor and a second transistor, wherein the second transistor includes a channel region comprising an oxide semiconductor layer, and wherein the oxide semiconductor layer is formed using an In—
Ga—
Zn—
O-based oxide semiconductor material. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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Specification