Nonvolatile memory device, operating method thereof and memory system including the same
First Claim
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1. A method of operating a non-volatile memory device, the method comprising:
- performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block; and
verifying the erasing operation to the memory cells comprising;
verifying the erasing operation to first memory cells associated with a first string selection line (SSL) line of the plurality of SSLs;
when verifying the erasing operation to the first memory cells associated. with the first SSL line fails, performing the erasing operation to the memory cells associated with the plurality of SSLs while holding a SSL address for the first SSL line; and
when verifying the erasing operation to the first memory cells passes, verifying the erasing operation to second memory cells associated with a second SSL line.
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Abstract
A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.
518 Citations
32 Claims
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1. A method of operating a non-volatile memory device, the method comprising:
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performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block; and verifying the erasing operation to the memory cells comprising; verifying the erasing operation to first memory cells associated with a first string selection line (SSL) line of the plurality of SSLs; when verifying the erasing operation to the first memory cells associated. with the first SSL line fails, performing the erasing operation to the memory cells associated with the plurality of SSLs while holding a SSL address for the first SSL line; and when verifying the erasing operation to the first memory cells passes, verifying the erasing operation to second memory cells associated with a second SSL line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A non-volatile memory device comprising:
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a memory cell array comprising memory cells associated with a plurality of string selection lines (SSLs); a voltage generating unit configured to generate an erase voltage for performing an erasing operation to the memory cells associated with the SSLs, the memory cells associated with the plurality of SSLs constituting a memory block; and a control logic configured to hold an SSL address for one of the plurality of SSLs when verifying the erasing operation to memory cells associated with the one of the plurality of SSLs fails while performing the erasing operation to the memory cells associated to the plurality of SSLs. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24)
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25. A method of verifying an erasing operation in a non-volatile memory device,
the method comprising: -
performing an erasing operation to a memory block including memory cells associated with at least two string selection lines (SSLs) including a first string selection line (SSL) and the second string selection line (SSL); selecting the first SSL while not selecting a second SSL from at least two SSLs constituting the memory block; verifying the erasing operation to memory cells connected to word lines associated with the selected first SSL; selecting the second SSL while not selecting the first SSL; and verifying the erasing operation to memory cells connected to word lines associated with the selected second SSL. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32)
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Specification