Method of operating semiconductor memory device with floating body transistor using silicon controlled rectifier principle
First Claim
1. A semiconductor memory cell comprising:
- a floating body region configured to be charged to a level indicative of a state of the memory cell;
a first region in electrical contact with said floating body region;
a second region in electrical contact with said floating body region and spaced apart from said first region;
a gate positioned between said first and second regions;
a buried layer region in electrical contact with said floating body region, below said first and second regions, spaced apart from said first and second regions; and
a substrate region configured to inject charge into said floating body region to hold the state of said memory cell.
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Abstract
A method of maintaining the data state of a semiconductor dynamic random access memory cell is provided, wherein the memory cell comprises a substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type; a second region having the second conductivity type, the second region being spaced apart from the first region; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region having the first conductivity type; and a gate positioned between the first and second regions and adjacent the body region.
256 Citations
27 Claims
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1. A semiconductor memory cell comprising:
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a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region;
a second region in electrical contact with said floating body region and spaced apart from said first region;a gate positioned between said first and second regions;
a buried layer region in electrical contact with said floating body region, below said first and second regions, spaced apart from said first and second regions; anda substrate region configured to inject charge into said floating body region to hold the state of said memory cell. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor memory cell comprising:
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a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a gate positioned between said first and second regions; a buried layer region in electrical contact with said floating body region, below said first and second regions, spaced apart from said first and second regions; and a substrate region configured to inject charge into said floating body region, wherein;
said substrate region, said buried layer region, said floating body region, and either of said first or second regions form a silicon controlled rectifier device. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16)
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17. A semiconductor memory array comprising:
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a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes;
a floating body region configured to be charged to a level indicative of a state of the memory cell;a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a gate positioned between said first and second regions; a buried layer region in electrical contact with said floating body region, below said first and second regions, spaced apart from said first and second regions; and a substrate region configured to inject charge into or extract charge out of said floating body region to hold said state of the memory cell. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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Specification