Dual function compatible non-volatile memory device

• US 8,559,261 B2
• Filed: 08/23/2012
• Issued: 10/15/2013
• Est. Priority Date: 12/20/2007
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Kim, Jin-Ki
• Primary Examiner(s): Lam, David
• Application Number:
  US13/592,953
• Publication Number:
  US 20120320693A1
• Time in Patent Office: 418 Days
• Field of Search: 365/191, 365/226, 365/233.1, 365/233.5
• US Class Current: 365/226
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physical ports and core circuits of the memory device are asynchronous and synchronous input and output signal paths or circuits. The signal paths include shared or dedicated buffers coupled to the ports, asynchronous and synchronous command decoders, a network of switches, and a mode detector. The mode detector determines the operating mode of the dual function memory device from a port, and provides the appropriate switch selection signal. The network of switches routes the input or output signals through the asynchronous or synchronous circuits in response to the switch selection signal. The appropriate command decoder interprets the input signals and provides common control logic with the necessary signals for initiating the corresponding operation.

Claims

1. A memory system comprising:

a memory controller for providing control signals having a first signal function assignment and second signal function assignment; and

a plurality of memory devices each configurable for receiving one of the first signal function assignment and the second signal function assignment in response to a port biased to a power supply voltage during a power up sequence, each of the plurality of memory devices configured for receiving the other of the first signal function assignment and the second signal function assignment when the port is biased to another power supply voltage during the power up sequence.

2. The memory device of claim 1, wherein the port is part of the first signal function assignment and is unused in the second function assignment.

3. The memory device of claim 1, wherein the port is unused in both the first signal function assignment and the second function assignment.

4. The memory device of claim 1, wherein the port is physically bonded to the power supply voltage.

5. The memory device of claim 1, wherein the port is statically held at the power supply voltage by a circuit.