Data reproduction circuit

• US 8,559,578 B2
• Filed: 04/14/2011
• Issued: 10/15/2013
• Est. Priority Date: 09/16/2005
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Tamura, Hirotaka
• Primary Examiner(s): DEPPE, BETSY LEE
• Application Number:
  US13/087,165
• Publication Number:
  US 20110249519A1
• Time in Patent Office: 915 Days
• Field of Search: 375/354, 375/355, 375/271, 375/373, 375/375, 375/376, 375/371
• US Class Current: 375/355
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

This is a data reproduction circuit for receiving data and reproducing the data and its clock which has an over-sampling determination circuit for sampling the received data by a clock with frequency higher than the data rate of the received data and converting the sampled data into digital signals, a circuit for selecting and outputting the reproduced data, a phase error detection circuit for detecting a phase error from its timing deviation with the received data, based on the reproduced clock, a data selection circuit for adjusting its phase, based on the output of the phase error detection circuit, a phase adjustment circuit for adjusting the phase of the reproduced clock to reproduce a new clock and a clock generation circuit for supplying the over-sampling determination circuit and the data selection circuit with the newly reproduced clock.

Claims

1. A data reproduction circuit for receiving data and reproducing data and a clock, the data reproduction circuit comprising;

a first clock generation circuit for generating a clock with a frequency higher than a data rate of the received data, based on a reference clock;

an over-sampling determination circuit for sampling the received data by the clock generated by the first clock generation circuit, so as to convert the received data into digital signals;

a data selection circuit having a circuit for reproducing data from the digital signals based on a first reproduced clock and for outputting the data, and having a phase/frequency error detection circuit for detecting a phase error and a frequency error from a timing difference between the first reproduced clock and the digital signals so as to generate and output an adjustment signal based on the phase error and the frequency error; and

a second clock generation circuit having a phase/frequency adjustment circuit for adjusting a phase and a frequency of the first reproduced clock by using the adjustment signal,

wherein the second clock generation circuit provides the first reproduced clock having an adjusted phase and an adjusted frequency to the data selection circuit.

2. The data reproduction circuit according to claim 1, wherein the phase/frequency adjustment circuit is a phase interpolator, and

wherein the data reproduction circuit further comprises a digital filter for generating a weighting signal which controls the phase interpolator, based on the adjustment signal of the phase/frequency error detection circuit and for outputting the weighting signal to the phase interpolator.

3. The data reproduction circuit according to claim 1, wherein the phase/frequency error detection circuit detects a data change timing of the digital signals based on the first reproduced clock, generates a phase signal from the change timing, converts the phase signal into a pointer signal that indicates movement of the phase signal,

and outputs the pointer signal as the adjustment signal in order to adjust the phase of the first reproduced clock.