Shift register
First Claim
1. A shift register comprising:
- unit circuits in cascade connection,each unit circuit including,an output transistor provided between a clock terminal and an output terminal, the output transistor configured to switch between passing and blocking of a clock signal, provided to the clock terminal, according to a gate potential applied to a gate of the output transistor; and
one or more control transistors each having a first conduction terminal, a second conduction terminal and a gate, the first conduction terminal of each control transistor being connected to the gate of the output transistor, the one or more control transistors including a first control transistor configured to reduce a leakage current during a clock passing period in which the output transistor is in an ON state and the clock signal has a high level potential, whereinduring the clock passing period,the gate potential of the output transistor is higher than the high-level potential of the clock signal,a low-level potential is applied to the gate of the first control transistor to turn the first control transistor to an OFF state, anda low-level potential is applied to the second conduction terminal of the first control transistor; and
the first control transistor has a channel length that is longer than a channel length of the output transistor.
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Accused Products
Abstract
Provided is a shift register configured by cascade connecting unit circuits each including a bootstrap circuit. In at least one example embodiment, for the unit circuits, a time period during which a transistor is in an ON state and a clock signal is high level corresponds to a clock passing period. Among transistors whose one conduction terminal is connected to a gate of the transistor, channel lengths of transistors configured such that a low-level potential is fed to gates of the transistors to turn the transistors to an OFF state in the clock passing period and that a low-level potential is applied to the conduction terminal of the transistors in the clock passing period are made longer than the channel length of the transistor. With this, it is possible to reduce a leakage current in the clock passing period, and to prevent the fluctuation of a gate potential of the transistor and dullness in an output signal from occurring.
17 Citations
16 Claims
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1. A shift register comprising:
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unit circuits in cascade connection, each unit circuit including, an output transistor provided between a clock terminal and an output terminal, the output transistor configured to switch between passing and blocking of a clock signal, provided to the clock terminal, according to a gate potential applied to a gate of the output transistor; and one or more control transistors each having a first conduction terminal, a second conduction terminal and a gate, the first conduction terminal of each control transistor being connected to the gate of the output transistor, the one or more control transistors including a first control transistor configured to reduce a leakage current during a clock passing period in which the output transistor is in an ON state and the clock signal has a high level potential, wherein during the clock passing period, the gate potential of the output transistor is higher than the high-level potential of the clock signal, a low-level potential is applied to the gate of the first control transistor to turn the first control transistor to an OFF state, and a low-level potential is applied to the second conduction terminal of the first control transistor; and the first control transistor has a channel length that is longer than a channel length of the output transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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Specification
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- Resources
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Current AssigneeSharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
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Original AssigneeSharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
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InventorsKikuchi, Tetsuo, Tanaka, Shinya, Yamasaki, Chikao, Shimada, Junya
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Primary Examiner(s)Lam, Tuan T
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Application NumberUS13/264,828Publication NumberTime in Patent Office1,390 DaysField of SearchNoneUS Class Current377/64CPC Class CodesG09G 2300/0426 Layout of electrodes and co...G09G 2310/0267 Details of drivers for scan...G09G 2310/0286 Details of a shift register...G09G 2310/0291 Details of output amplifier...G09G 2330/021 Power management, e.g. powe...G09G 3/20 for presentation of an asse...G09G 3/3677 suitable for active matrice...G11C 19/28 using semiconductor element...
