Optimizing EDRAM refresh rates in a high performance cache architecture

• US 8,560,767 B2
• Filed: 07/11/2012
• Issued: 10/15/2013
• Est. Priority Date: 06/24/2010
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bronson, Timothy C., Fee, Michael, O'Neill, Arthur J. Jr., Swaney, Scott B.
• Primary Examiner(s): Gu, Shawn X
• Application Number:
  US13/546,687
• Publication Number:
  US 20120278548A1
• Time in Patent Office: 461 Days
• Field of Search: None
• US Class Current: 711/106
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811

Abstract

Embodiments relate to embedded Dynamic Random Access Memory (eDRAM) refresh rates in a high performance cache architecture. An aspect includes receiving a plurality of first signals. A refresh request is transmitted via a refresh requestor to a cache memory at a first refresh rate which includes an interval, including a subset of the first signals. The first refresh rate corresponds to a maximum refresh rate. A refresh counter is reset based on receiving a second signal. The refresh counter is incremented after receiving each of a number of refresh requests. A current count is transmitted from a refresh counter to the refresh requestor based on receiving a third signal. The refresh request is transmitted at a second refresh rate, which is less than the first refresh rate. The refresh request is transmitted based on receiving the current count from the refresh counter and determining that the current count is greater than a refresh threshold.

Claims

1. A method for optimizing refresh request transmission rates in a high performance cache comprising:

receiving a plurality of first signals;

transmitting, via a refresh requestor, a refresh request to a cache memory at a first refresh rate, the first refresh rate comprising an interval, the interval comprising a subset of the plurality of first signals, the first refresh rate corresponding to a maximum refresh rate;

resetting a refresh counter based on receiving a second signal;

incrementing the refresh counter based on receiving each of a plurality of refresh requests from the refresh requestor;

transmitting a current count from the refresh counter to the refresh requestor based on receiving a third signal; and

transmitting a refresh request at a second refresh rate, the second refresh rate less than the first refresh rate, based on receiving the current count from the refresh counter and determining that the current count is greater than a refresh threshold.

2. The method of claim 1 wherein the cache memory is operatively coupled to the refresh requestor and the refresh counter.

3. The method of claim 1, wherein the cache memory comprises enhanced dynamic random access memory (eDRAM).

4. The method of claim 1, wherein the plurality of first signals are central processing unit (CPU) cycles received from a node.

5. The method of claim 1, wherein the second signal is a time of day (TOD) interval pulse.

6. The method of claim 1, wherein the second signal is a time of day (TOD) active signal.

7. The method of claim 1, wherein the third signal is a time of day (TOD) interval pulse, the third signal a next signal received after the second signal.

8. The method of claim 1, wherein the refresh requestor is further configured to transmit refresh requests at the first refresh rate based on receiving the current count from the refresh counter and determining that a number of refresh requests transmitted between the second signal and the third signal were sent at a varying interval.