Method and apparatus for indicating mask information

• US 8,560,797 B2
• Filed: 03/15/2012
• Issued: 10/15/2013
• Est. Priority Date: 10/10/1997
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Barth, Richard M., Ware, Frederick A., Stark, Donald C., Hampel, Craig E., Davis, Paul G., Abhyankar, Abhijit M., Nguyen, David, Gasborro, James A.
• Primary Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US13/421,701
• Publication Number:
  US 20120173810A1
• Time in Patent Office: 579 Days
• Field of Search: 711/105, 711/167, 711/E12.001, 711/106
• US Class Current: 711/167
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/2218 Late write
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit, over a first plurality of wires, to the DRAM a first code to indicate that first data is to be written to the DRAM and a column address to indicate a column location of a memory core in the DRAM where the first data is to be written. The interface is further to transmit a second code to indicate whether mask information for the first data will be sent to the DRAM. If the second code indicates that mask information will be sent, a portion of the column address and a portion of the mask information are sent after the second code is sent. The interface is further to transmit to the DRAM, over a second plurality of wires separate from the first plurality of wires, the first data.

Claims

1. An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising:

an interface to transmit;

over a first plurality of wires, to the DRAM;

a first code to indicate that first data is to be written to the DRAM, wherein the first code is to be registered by the DRAM at one or more edges of an external clock signal received by the DRAM;

a column address to indicate a column location of a memory core in the DRAM where the first data is to be written, wherein the column address is to be registered by the DRAM at one or more edges of the external clock signal;

a second code to indicate whether mask information for the first data will be sent to the DRAM, the second code being sent over a subset of wires of the first plurality of wires, wherein;

the mask information indicates whether certain portions of the first data is to be transmitted to the DRAM; and

if the second code indicates that mask information will be sent, a portion of the column address and a portion of the mask information are sent over the subset of wires after the second code is sent over the subset of wires, wherein the mask information is to be registered by the DRAM at one or more edges of the external clock signal; and

over a second plurality of wires separate from the first plurality of wires, to the DRAM, the first data.

2. The apparatus of claim 1, wherein the interface is to transmit to the DRAM, a third code to indicate that second data is to be written to or read from the DRAM, wherein the third code is to be registered by the DRAM at a first edge of the external clock after the first code is registered, and

wherein a portion of the first data is to be registered by the DRAM at a point in time coincident with the first edge of the external clock.

3. The apparatus of claim 1, wherein two consecutive bits of the portion of the mask information are to be transmitted during a clock cycle of the external clock signal.

4. The apparatus of claim 1, wherein the interface is to transmit to the DRAM:

a first bank address that is associated with a first command that specifies activation of a row of memory cells, wherein the first bank address identifies a bank of a plurality of memory cell banks in which to perform the activation;

a second bank address that is associated with the column address; and

a second command that specifies a write operation to be performed, wherein the second bank address identifies a bank of a plurality of memory cell banks in which to perform the write operation.

5. The apparatus of claim 4, wherein:

the first command and the first bank address are to be transmitted in a first packet over the first plurality of wires; and

the second command, the second bank address, the column address, the first code and the second code are to be transmitted in a second packet over the first plurality of wires.

6. The apparatus of claim 4, wherein:

a first portion of the first plurality of wires are to transmit the first command and the first bank address; and

a second portion of the first plurality of wires are to transmit the second command, the second bank address, the column address, the first code and the second code, wherein the second portion of the first plurality of wires comprises the subset of the first plurality of wires.

7. The apparatus of claim 6, wherein:

the first portion of the first plurality of wires is a primary interconnect consisting of three signal lines;

the second portion of the first plurality of wires is a secondary interconnect consisting of five signal lines; and

the second plurality of wires is a data bus consisting of eighteen signal lines.

8. A dynamic random access memory (DRAM) device, comprising:

clock circuitry for receiving an external clock signal;

a first interface to receive;

a first code to indicate that first data is to be written to the DRAM, wherein the first code is registered by the DRAM at one or more edges of the external clock signal;

a column address to indicate a column location of a memory core in the DRAM where the first data is to be written, wherein the column address is registered by the DRAM at one or more edges of the external clock signal;

a second code to indicate whether mask information for the first data will be sent to the DRAM, the second code being sent over a subset of wires of the first plurality of wires, wherein;

the mask information indicates whether certain portions of the first data is transmitted to the DRAM; and

if the second code indicates that mask information will be sent, a portion of the column address and a portion of the mask information are received over the subset of wires after the second code is received over the subset of wires, wherein the mask information be registered by the DRAM at one or more edges of the external clock signal; and

a second interface, separate from the first interface, to receive the first data.

9. The DRAM device of claim 8, wherein the first interface is to receive a third code to indicate that second data is to be written to or read from the DRAM, wherein the third code is registered by the DRAM at a first edge of the external clock after the first code is registered, and

wherein a portion of the first data is registered by the DRAM at a point in time coincident with the first edge of the external clock.

10. The DRAM device of claim 8, wherein two consecutive bits of the portion of the mask information are received during a clock cycle of the external clock signal.

11. The DRAM device of claim 8, wherein the first interface is to receive:

a first bank address that is associated with a first command that specifies activation of a row of memory cells, wherein the first bank address identifies a bank of a plurality of memory cell banks in which to perform the activation;

a second bank address that is associated with the column address; and

a second command that specifies a write operation to be performed, wherein the second bank address identifies a bank of a plurality of memory cell banks in which to perform the write operation.

12. A method of operation of an apparatus that controls a dynamic random access memory (DRAM), the method comprising:

over a first plurality of wires;

transmitting, to the DRAM, a first code to indicate that first data is to be written to the DRAM, wherein the first code is to be registered by the DRAM at one or more edges of an external clock signal received by the DRAM;

transmitting, to the DRAM, a column address to indicate a column location of a memory core in the DRAM where the first data is to be written, wherein the column address is to be registered by the DRAM at one or more edges of the external clock signal;

transmitting, to the DRAM, a second code to indicate whether mask information for the first data will be sent to the DRAM, the second code being sent over a subset of wires of the first plurality of wires, wherein;

the mask information indicates whether certain portions of the first data is to be transmitted to the DRAM; and

if the second code indicates that mask information will be sent, a portion of the column address and a portion of the mask information are sent over the subset of wires after the second code is sent over the subset of wires, wherein the mask information is to be registered by the DRAM at one or more edges of the external clock signal; and

over a second plurality of wires separate from the first plurality of wires, transmitting, to the DRAM, the first data.

13. The method of claim 12, further comprising transmitting, to the DRAM, a third code to indicate that second data is to be written to or read from the DRAM, wherein the third code is to be registered by the DRAM at a first edge of the external clock after the first code is registered and a portion of the first data is to be registered by the DRAM at a point in time coincident with the first edge of the external clock.

14. The method of claim 12, further comprising transmitting, to the DRAM, two consecutive bits of the portion of the mask information during a clock cycle of the external clock signal.

15. The method of claim 12, further comprising transmitting, to the DRAM:

a first bank address that is associated with a first command that specifies activation of a row of memory cells, wherein the first bank address identifies a bank of a plurality of memory cell banks in which to perform the activation;

a second bank address that is associated with the column address; and

a second command that specifies a write operation to be performed, wherein the second bank address identifies a bank of a plurality of memory cell banks in which to perform the write operation.

16. A method of operation of a dynamic random access memory (DRAM) device, the method comprising:

receiving an external clock signal;

receiving, at a first interface, a first code to indicate that first data is to be written to the DRAM, wherein the first code is registered at one or more edges of the external clock signal;

receiving, at the first interface, a column address to indicate a column location of a memory core in the DRAM where the first data is to be written, wherein the column address is registered by the DRAM at one or more edges of the external clock signal;

receiving, at the first interface, a second code to indicate whether mask information for the first data will be sent to the DRAM, the second code being sent over a subset of wires of the first plurality of wires, wherein;

the mask information indicates whether certain portions of the first data is transmitted to the DRAM; and

if the second code indicates that mask information will be sent, a portion of the column address and a portion of the mask information are received over the subset of wires after the second code is received over the subset of wires, wherein the mask information be registered by the DRAM at one or more edges of the external clock signal; and

receiving at a second interface that is separate from the first interface, the first data.

17. The method of claim 16, further comprising receiving, at the first interface, a third code to indicate that second data is to be written to or read from the DRAM, wherein the third code is registered by the DRAM at a first edge of the external clock after the first code is registered and a portion of the first data is registered by the DRAM at a point in time coincident with the first edge of the external clock.

18. The method of claim 16, further comprising receiving, at the DRAM, two consecutive bits of the portion of the mask information during a clock cycle of the external clock signal.

19. The method of claim 16, further comprising receiving, at the first interface:

a first bank address that is associated with a first command that specifies activation of a row of memory cells, wherein the first bank address identifies a bank of a plurality of memory cell banks in which to perform the activation;

a second bank address that is associated with the column address; and

a second command that specifies a write operation to be performed, wherein the second bank address identifies a bank of a plurality of memory cell banks in which to perform the write operation.