Reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device

• US 8,560,804 B2
• Filed: 09/14/2010
• Issued: 10/15/2013
• Est. Priority Date: 09/14/2009
• Status: Active Grant

• Current Assignee: BiTMICRO, LLC (BiTMICRO Networks, Inc.)
• Original Assignee: BiTMICRO Networks, Inc.
• Inventors: Chong, Ryan C., Arcedera, Mark Ian A., Lanuza, Reyjan C., Lukban, Jose Miguel N., Bruce, Rolando H.
• Primary Examiner(s): ELMORE, STEPHEN C
• Application Number:
  US12/882,059
• Publication Number:
  US 20110113186A1
• Time in Patent Office: 1,127 Days
• Field of Search: 711/202, 711/103, 711/156, 711/158, 711/165, 711/170, 365/185.33
• US Class Current: 711/202
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed.

Claims

1. An electronic storage device-enabled method of reducing erase cycles in an electronic storage device that uses erase-limited memory devices, including erase-limited memory devices that each include a plurality of blocks, the method comprising:

creating a first flop that includes at least one flop section, including a first flop section and a second flop section;

mapping a first address to said first flop;

reading said flop sections from said first flop using a section selection sequence;

storing data associated with said first address in said first flop by writing said data into said first flop section and storing a first value representing said first flop section location into a valid flop section location;

if said data is changed, storing said changed data into said second flop section, storing and assigning said first flop section with an invalid status, storing said changed data in said second flop section, and assigning a valid status to said changed data; and

limiting said data to have a data size that is no more than the flop section size of said at least one flop section.

2. The method of claim 1, wherein said creating a first flop further includes:

erasing a first block associated with a first erase-limited memory device;

associating said first block to said first address; and

partitioning said first block into said first flop section and said second flop section.

3. The method of claim 1, wherein said creating a first flop further includes:

erasing a first block and a second block that are associated with a first erase-limited memory device;

associating said first and second blocks to said first address; and

partitioning said first block into at least said first flop section and said second block into at least said second flop section.

4. The method of claim 1, wherein said creating a first flop further includes erasing a first block that is associated with a first flash memory device.

5. The method of claim 4, wherein said first flop section includes a flop section size that is equal to the size of a minimum writable location defined for said first block.

6. The method of claim 5, wherein said minimum writable location is a partial page of said first block.

7. The method of claim 5, wherein said minimum writable location is a page of said first block.

8. An electronic storage device-enabled method of reducing erase cycles in an electronic storage device that uses erase-limited memory devices, including at least one erase-limited memory device, the method comprising:

initializing a first flop from an erase-limited memory device by at least mapping a first address to a first flop, erasing a first flop block, and creating a plurality of flop sections from said first flop block;

limiting memory device write operations of data associated with said first address to only a flop section that has not been previously used to store said data after initialization of said first flop; and

re-initializing said first flop block after all of said plurality of flop sections from said first flop block have been used in said write operations.

9. The method of claim 8, wherein said first flop includes a first block address and a second block address.

10. The method of claim 8, further includes:

using a mapping structure and a pointer to point said first address to a second address; and

using said pointer as said data.

11. The method of claim 10, further includes using a host address as said first address, and a local address as said second address.

12. The method of claim 10, further includes using a host LEA (logical block address) address as said first address, and a local physical address as said second address.

13. The method of claim 8, wherein said first flop block is a first flash block from said erase-limited memory device.

14. The method of claim 13, wherein said at least one flop block further includes a second flop block.

15. The method of claim 13, wherein said first flop includes flop sections from a second memory device.

16. The method of claim 13, wherein said second flop block is from a second erase-limited memory device.

17. The method of claim 8, further includes:

limiting said data to have a data size that is no more than the flop section size of said at least one flop section.

18. The method of claim 8, further includes using a NAND flash memory device (Not And flash memory device) as said erase-limited memory device.

19. An electronic storage device disposed to minimize erase cycles in at least one erase-limited memory device, comprising:

program code;

a means for executing said program code;

a memory subsystem coupled to a plurality of memory devices that includes at least one erase-limited memory device, and responsive to said processing system;

said program code for causing said means for executing;

to initialize a first flop from an erase-limited memory device from said at least one erase-limited memory device by at least mapping a first address to a first flop, erasing a first flop block, and creating a plurality of flop sections from said first flop block;

to limit memory device write operations of data associated with said first address to only a flop section that has not been previously used to store said data after initialization of said first flop; and

to re-initializing said first flop block after all of said plurality of flop sections associated with said first flop block have been used in said write operations.

20. The electronic storage device in claim 19:

further including an IO (input/output) interface disposed to receive a memory transaction request; and

said means for executing includes a processor coupled to a working memory, to said memory subsystem; and

said IO interface.

21. The electronic storage device in claim 19, further including a multilevel structure that includes control data disposed to point to said first flop.

22. An apparatus for reducing erase cycles in an electronic storage device that uses erase-limited memory devices, including erase-limited memory devices that each include a plurality of blocks, the apparatus comprising:

means for initializing a first flop from an erase-limited memory device by at least mapping a first address to a first flop, erasing at least one flop block associated with said first flop; and

creating a plurality of flop sections from said first flop block;

means for limiting memory device write operations of data associated with said first address to only a flop section that has not been previously used to store said data after initialization of said first flop; and

means for re-initializing a first flop block after all of said plurality of flop sections have been used in said write operations.

23. A computer readable, non-transient physical storage medium comprising machine executable instructions stored therein, wherein the instructions, when executed by a processing system, are adapted to cause a method of reducing erase cycles in an electronic storage device that uses erase-limited memory devices, including erase-limited memory devices that each include a plurality of blocks, said method comprising:

initializing a first flop from an erase-limited memory device by at least mapping a first address to a first flop, erasing a first flop block, and creating said plurality of flop sections from said first flop block; and

limiting memory device write operations of data associated with said first address to only a flop section that has not been previously used to store said data after initialization of said first flop; and

re-initializing said first flop block after all of said plurality of flop sections have been used in said write operations.

24. An electronic storage device disposed to minimize erase cycles in at least one erase-limited memory device, comprising:

program code;

a processing system disposed to execute said program code;

a memory subsystem coupled to a plurality of memory devices that includes at least one erase-limited memory device, and responsive to said processing system;

said program code for causing said processing system;

to initialize a first flop from an erase-limited memory device from said at least one erase-limited memory device by at least mapping a first address to a first flop, erasing a first flop block, and creating a plurality of flop sections from said first flop block;

to limit memory device write operations of data associated with said first address to only a flop section that has not been previously used to store said data after initialization of said first flop; and

to re-initializing said first flop after all of said plurality of flop sections have been used in said write operations.