Thread fairness on a multi-threaded processor with multi-cycle cryptographic operations

• US 8,560,814 B2
• Filed: 05/04/2010
• Issued: 10/15/2013
• Est. Priority Date: 05/04/2010
• Status: Active Grant

• Current Assignee: Oracle International Corporation (Oracle Corporation)
• Original Assignee: Oracle International Corporation (Oracle Corporation)
• Inventors: Golla, Robert T., Olson, Christopher H., Grohoski, Gregory F.
• Primary Examiner(s): Caldwell, Andrew
• Assistant Examiner(s): Xiao, Yuqing
• Application Number:
  US12/773,278
• Publication Number:
  US 20110276783A1
• Time in Patent Office: 1,260 Days
• Field of Search: 712/1, 712/201, 712219-221, 712/226, 712/229, 712/245, 718102-103, 718107-108
• US Class Current: 712/220
• CPC Class Codes: G06F 2209/507 Low-level
• CPC Class Codes: G06F 9/30007 to perform operations on data operands
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3889 controlled by multiple instructions, e.g. MIMD, decoupled access or execute
• CPC Class Codes: G06F 9/5011 the resources being hardware resources other than CPUs, Servers and Terminals

Abstract

Systems and methods for efficient execution of operations in a multi-threaded processor. Each thread may include a blocking instruction. A blocking instruction blocks other threads from utilizing hardware resources for an appreciable amount of time. One example of a blocking type instruction is a Montgomery multiplication cryptographic instruction. Each thread can operate in a thread-based mode that allows the insertion of stall cycles during the execution of blocking instructions, during which other threads may utilize the previously blocked hardware resources. At times when multiple threads are scheduled to execute blocking instructions, the thread-based mode may be changed to increase throughput for these multiple threads. For example, the mode may be changed to disallow the insertion of stall cycles. Therefore, the time for sequential operation of the blocking instructions corresponding to the multiple threads may be reduced.

Claims

1. A microprocessor comprising:

an instruction pipeline configured to concurrently process instructions corresponding to a plurality of threads, wherein the instruction pipeline comprises one or more hardware (HW) resource groups each configured to execute instructions; and

control circuitry;

wherein for a given HW resource group of the one or more HW resource groups, the control circuitry is configured to;

identify at least two active threads configured to utilize the given HW resource group and execute an instruction of a first type, the given HW resource group being configured to support only one of the at least two active threads at a given time;

set a thread mode for a first thread of the at least two active threads to a first mode which causes an issued instruction of the first type to execute with one or more added stalls within the given HW resource group, in response to a condition being met, said condition comprising determining the first thread is associated with an instruction of the first type and a second thread of the at least two active threads is not associated with an instruction of the first type; and

set the thread mode for the first thread to a second mode which causes the issued instruction of the first type to execute without said one or more added stalls within the given HW resource group, in response to said condition not being met.

2. The microprocessor as recited in claim 1, wherein the issued instruction of the first type is at least one of the following instructions:

a multi-precision multiplication cryptographic instruction, a Montgomery multiplication cryptographic instruction, and a Montgomery square cryptographic instruction.

3. The microprocessor as recited in claim 2, wherein the given HW resource group comprises at least a cryptographic functional unit and a non-cryptographic functional unit.

4. The microprocessor as recited in claim 1, wherein the instruction of the first type causes a plurality of functional units within the given HW resource group to be unavailable for execution for other instructions for a plurality of clock cycles.

5. The microprocessor as recited in claim 3, wherein determining a given thread is associated with an instruction of the first type comprises:

(i) determining the given thread is configured to execute an instruction of the first type, or (ii) determining the given thread has recently committed an instruction of the first type.

6. The microprocessor as recited in claim 5, wherein in response to determining the given thread has recently committed an instruction of the first type, the control circuitry is further configured to determine the given thread is no longer associated with an instruction of the first type by detecting the given thread has committed a number of instructions greater than a predetermined threshold, wherein the committed instructions do not include an instruction of the first type.

7. The microprocessor as recited in claim 1, wherein the issued instruction of the first type is executed for a first number of cycles before being stalled for a second number of cycles, wherein the first number of cycles is based on at least one of the following:

completion of a given number of execution cycles, completion of a predetermined operation, and a programmable value.

8. The microprocessor as recited in claim 1, wherein intermediate results of the issued instruction of the first type are temporarily stored prior to the one or more added stalls within the given HW resource group.

9. A method for use in a processor, the method comprising:

concurrently processing instructions corresponding to a plurality of threads, wherein processing utilizes one or more hardware (HW) resource groups each configured to execute instructions;

wherein for a given HW resource group of the one or more HW resource groups;

identifying at least two active threads configured to utilize the given HW resource group and execute an instruction of a first type, the given HW resource group being configured to support only one of the at least two threads at a given time;

setting a thread mode for a first thread of the at least two active threads to a first mode which causes an issued instruction of the first type to execute with one or more added stalls, in response to determining the first thread is associated with an instruction of the first type and a second thread of the at least two active threads is not associated with an instruction of the first type; and

setting the thread mode for the first thread to a second mode which causes the issued instruction of the first type to execute without said one or more added stalls within the given HW resource group, in response to said condition is not met.

10. The method as recited in claim 9, wherein the issued instruction of the first type is at least one of the following instructions:

a multi-precision multiplication cryptographic instruction, a Montgomery multiplication cryptographic instruction, and a Montgomery square cryptographic instruction.

11. The method as recited in claim 10, wherein the given HW resource group comprises at least a cryptographic functional unit and a non-cryptographic functional unit.

12. The method as recited in claim 11, further comprising:

identifying a third thread configured to utilize the given HW resource group; and

determining the third thread is not associated with an instruction of the first type, wherein the given HW resource group is configured to support each of the second thread and the third thread at a given time.

13. The method as recited in claim 11, wherein determining a given thread is associated with an instruction of the first type comprises:

(i) determining the given thread is configured to execute an instruction of the first type, or (ii) determining the given thread has recently committed an instruction of the first type.

14. The method as recited in claim 13, wherein in response to determining the given thread has recently committed an instruction of the first type, further comprising determining the given thread is no longer associated with an instruction of the first type by detecting the given thread has committed a number of instructions greater than a predetermined threshold, wherein the committed instructions do not include an instruction of the first type.

15. The method as recited in claim 9, wherein to identify a particular thread configured to utilize the given HW resource group, the method further comprises determining an instruction of the particular thread is scheduled for execution by the given HW resource group or an instruction of the particular thread is being executed by the given HW resource group.

16. The method as recited in claim 9, wherein in response to detecting the thread mode for the first thread is set to the first mode, the method further comprises utilizing the given HW resource group by an instruction in the second thread during the one or more added stalls of the issued instruction of the first type in the first thread.

17. A non-transitory computer readable storage medium storing program instructions, wherein the program instructions are executable to:

concurrently process instructions corresponding to a plurality of threads, wherein processing utilizes one or more hardware (HW) resource groups each configured to execute instructions;

wherein for a given HW resource group of the one or more HW resource groups;

identify at least two active threads configured to utilize the given HW resource group and execute an instruction of a first type, the given HW resource group being configured to support only one of the at least two threads at a given time;

set a thread mode for a first thread of the at least two active threads to a first mode which causes an issued instruction of the first type to execute with one or more added stalls, in response to determining the first thread is associated with an instruction of the first type and a second thread of the at least active two threads is not associated with an instruction of the first type; and

set the thread mode for the first thread to a second mode which causes the issued instruction of the first type to execute without said one or more added stalls within the given HW resource group, in response to said condition is not met.

18. The non-transitory computer readable storage medium as recited in claim 17, wherein the issued instruction of the first type is at least one of the following instructions:

a multi-precision multiplication cryptographic instruction, a Montgomery multiplication cryptographic instruction, and a Montgomery square cryptographic instruction.

19. The non-transitory computer readable storage medium as recited in claim 18, wherein the given HW resource group comprises at least a cryptographic functional unit and a non-cryptographic functional unit.

20. The non-transitory computer readable storage medium as recited in claim 19, wherein in response to detecting the thread mode for the first thread is set to the first mode, an instruction in the second thread utilizes the given HW resource group during the one or more added stalls of the issued instruction of the first type in the first thread.