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Timing-aware test generation and fault simulation

  • US 8,560,906 B2
  • Filed: 10/31/2011
  • Issued: 10/15/2013
  • Est. Priority Date: 04/27/2006
  • Status: Active Grant
First Claim
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1. A method of generating test patterns for testing an integrated circuit, comprising:

  • identifying two or more possible fault activation conditions in an integrated circuit design, the possible fault activation conditions being capable of activating a targeted delay fault at a fault site through a gate in the integrated circuit design;

    selecting one of the possible fault activation conditions using a weighted random selection procedure in which the weight wi for a respective possible fault activation condition I in the weighted random selection procedure corresponds to either;

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