Timing-aware test generation and fault simulation

• US 8,560,906 B2
• Filed: 10/31/2011
• Issued: 10/15/2013
• Est. Priority Date: 04/27/2006
• Status: Active Grant

• Current Assignee: Siemens Industry Software Inc. (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Lin, Xijiang, Tsai, Kun-Han, Kassab, Mark, Wang, Chen, Rajski, Janusz
• Primary Examiner(s): NGUYEN, STEVE N
• Application Number:
  US13/285,899
• Publication Number:
  US 20120174049A1
• Time in Patent Office: 715 Days
• Field of Search: 714/738, 714/724
• US Class Current: 714/738
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318328 for delay tests
• CPC Class Codes: G01R 31/31835 Analysis of test coverage or failure detectability
• CPC Class Codes: G01R 31/318357 Simulation computer simulation of digital circuits G06F30/3308
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30

Abstract

Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.

Claims

1. A method of generating test patterns for testing an integrated circuit, comprising:

identifying two or more possible fault activation conditions in an integrated circuit design, the possible fault activation conditions being capable of activating a targeted delay fault at a fault site through a gate in the integrated circuit design;

selecting one of the possible fault activation conditions using a weighted random selection procedure in which the weight w_i for a respective possible fault activation condition I in the weighted random selection procedure corresponds to either;

2. The method of claim 1, wherein the weighted random selection procedure favors paths with longer arrival times to the targeted delay fault site over paths with shorter arrival times to the targeted delay fault site.

3. The method of claim 1, wherein the weighted random selection procedure favors paths with shorter arrival times to the targeted delay fault site over paths with longer arrival times to the targeted delay fault site.

4. The method of claim 1, wherein the computed weight for a respective one of the possible fault activation conditions indicates the probability that the respective one of the possible fault activation conditions will be selected by the weighted random selection procedure.

5. The method of claim 1, wherein the method further comprises computing activation times for one or more gates in the paths used with the possible fault activation conditions, and wherein the weighted random selection procedure is based at least in part on the computed activation times.

6. The method of claim 5, wherein the act of computing the activation times comprises using timing information from an SDF file.

7. The method of claim 1, further comprising selecting a fault propagation path for propagating a fault effect of the targeted delay fault to an observation point of the integrated circuit design using a weighted random selection procedure that favors fault propagation paths having longer propagation times over fault propagation paths having shorter propagation times.

8. The method of claim 1, further comprising selecting a fault propagation path for propagating a fault effect of the targeted delay fault to an observation point of the integrated circuit design using a weighted random selection procedure that favors fault propagation paths having shorter propagation times over fault propagation paths having longer propagation times.

9. One or more computer-readable memory or storage devices storing test pattern values generated by a method, the method comprising:

identifying two or more possible fault activation conditions in an integrated circuit design, the possible fault activation conditions being capable of activating a targeted delay fault at a fault site through a gate in the integrated circuit design;

selecting one of the possible fault activation conditions using a weighted random selection procedure in which the weight w_i for a respective possible fault activation condition I in the weighted random selection procedure corresponds to either;

10. One or more computer-readable memory or storage devices storing computer-executable instructions for causing a computer to perform a method, the method comprising:

identifying two or more possible fault activation conditions in an integrated circuit design, the possible fault activation conditions being capable of activating a targeted delay fault at a fault site through a gate in the integrated circuit design;

selecting one of the possible fault activation conditions using a weighted random selection procedure in which the weight w_i for a respective possible fault activation condition I in the weighted random selection procedure corresponds to either;

11. The one or more computer-readable memory or storage devices of claim 10, wherein the weighted random selection procedure favors paths with longer arrival times to the targeted delay fault site over paths with shorter arrival times to the targeted delay fault site.

12. The one or more computer-readable memory or storage devices of claim 10, wherein the weighted random selection procedure favors paths with shorter arrival times to the targeted delay fault site over paths with longer arrival times to the targeted delay fault site.

13. The one or more computer-readable memory or storage devices of claim 10, wherein the computed weight for a respective one of the possible fault activation conditions indicates the probability that the respective one of the possible fault activation conditions will be selected by the weighted random selection procedure.

14. The one or more computer-readable memory or storage devices of claim 10, wherein the method further comprises computing activation times for one or more gates in the paths used with the possible fault activation conditions, and wherein the weighted random selection procedure is based at least in part on the computed activation times.

15. The one or more computer-readable memory or storage devices of claim 14, wherein the act of computing the activation times comprises using timing information from an SDF file.

16. The one or more computer-readable memory or storage devices of claim 10, wherein the method further comprises selecting a fault propagation path for propagating a fault effect of the targeted delay fault to an observation point of the integrated circuit design using a weighted random selection procedure that favors fault propagation paths having longer propagation times over fault propagation paths having shorter propagation times.

17. The one or more computer-readable memory or storage devices of claim 10, wherein the method further comprises selecting a fault propagation path for propagating a fault effect of the targeted delay fault to an observation point of the integrated circuit design using a weighted random selection procedure that favors fault propagation paths having shorter propagation times over fault propagation paths having longer propagation times.