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Debugging external interface

  • US 8,560,907 B1
  • Filed: 08/12/2008
  • Issued: 10/15/2013
  • Est. Priority Date: 09/06/2007
  • Status: Active Grant
First Claim
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1. A memory controller comprising:

  • a first interface coupled to an external memory device;

    a second interface coupled to an external user device; and

    a processor operable to;

    test the first interface, said test comprising measuring;

    a timing differential characteristic of the external memory device and the first interface, anda timing margin by which a timing error is avoided during the test in response to a determination that the error has not yet occurred during the test;

    access stored data describing a physical layout of at least one device in response to an error received during said test and after said measuring of the timing margin, wherein the physical layout of the at least one device includes a physical layout of the memory controller,determine, based on the accessed stored data, and without user input, whether the physical layout of the at least one device caused the error, andprovide a result of said test to the external user device via the second interface.

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