Debugging external interface

• US 8,560,907 B1
• Filed: 08/12/2008
• Issued: 10/15/2013
• Est. Priority Date: 09/06/2007
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Thorne, Neil Kenneth
• Primary Examiner(s): NGUYEN, STEVE N
• Application Number:
  US12/190,573
• Time in Patent Office: 1,890 Days
• Field of Search: 714/718, 714/723, 714/725, 714/700, 714/745
• US Class Current: 714/745
• CPC Class Codes: G01R 31/31705 Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544
• CPC Class Codes: G01R 31/318519 Test of field programmable gate arrays [FPGA]
• CPC Class Codes: G06F 11/3656 using a specific debug interface
• CPC Class Codes: G11C 2029/0401 in embedded memories
• CPC Class Codes: G11C 2029/0403 during or with feedback to manufacture
• CPC Class Codes: G11C 29/10 Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

A memory controller has a first interface, for connection to an external memory device; a second interface, for connection to at least one other component; and a third JTAG interface, for connection to an external user device. The memory controller further includes a processor, which performs calibration processes, in order to synchronize operations of the memory controller and the external memory device, and also runs test software for testing operation of the first interface and the external memory device, and for providing test results to the external user device over the third interface. The memory controller further includes an internal memory, for storing the instructions defining the test software.

Claims

1. A memory controller comprising:

a first interface coupled to an external memory device;

a second interface coupled to an external user device; and

a processor operable to;

test the first interface, said test comprising measuring;

a timing differential characteristic of the external memory device and the first interface, and

a timing margin by which a timing error is avoided during the test in response to a determination that the error has not yet occurred during the test;

access stored data describing a physical layout of at least one device in response to an error received during said test and after said measuring of the timing margin, wherein the physical layout of the at least one device includes a physical layout of the memory controller,

determine, based on the accessed stored data, and without user input, whether the physical layout of the at least one device caused the error, and

provide a result of said test to the external user device via the second interface.

2. The memory controller of claim 1, further comprising an internal memory for storing instructions comprising software to be executed by the processor to produce the result of said test.

3. The memory controller of claim 2, wherein said software is initiated automatically on powering up.

4. The memory controller of claim 2, wherein said software is initiated automatically in response to detection of an operational problem.

5. The memory controller of claim 2, wherein said software is initiated in response to a user input.

6. The memory controller of claim 1, wherein the second interface is a JTAG interface.

7. The memory controller of claim 1, wherein the processor is further operable to perform a calibration process to synchronize operations of the memory controller and the external memory device.

8. The method of claim 1, wherein the processor is further operable to measure the timing margin based, at least in part, on data obtained from a previous calibration of the memory controller.

9. The method of claim 1, wherein the processor is further operable to test the first interface while the memory controller executes a function unrelated to the test.

10. A computer-readable product comprising a non-transitory machine readable medium on which is provided data for causing a programmable logic device to implement a memory controller method, the method comprising:

coupling a first interface with an external memory device;

coupling a second interface with an external user device;

testing the first interface for compatibility with the external memory device, said testing comprising measuring;

a timing differential characteristic of the external memory device and the first interface, and

a timing margin by which a timing error is avoided during the testing in response to a determination that the error has not yet occurred during the testing;

accessing stored data describing a physical layout of at least a portion of the programmable logic device in response to an error received during said testing and after said measuring of the timing margin;

determining, based on the accessed stored data, and without user input, whether the physical layout of the at least a portion of the programmable logic device caused the error; and

providing a result of the testing to the external user device via the second interface.

11. An electronic device comprising:

an interface controller comprising;

a first interface coupled to a device external to the interface controller;

a second interface coupled to an external user device; and

a processor, the processor operable to;

test the first interface for compatibility with the device external to the interface controller, said test comprising measuring a timing margin by which a timing error is avoided during the test in response to a determination that the error has not yet occurred during the test,

access stored data describing a physical layout of at least one device in response to an error received during said test and after said measuring of the timing margin, wherein the physical layout of the at least one device includes a physical layout of the interface controller,

determine, based on the accessed stored data, and without user input, whether the physical layout of the at least one device caused the error,

provide a result of said test to the external user device via the second interface, and

in response to a determination that the result of said test corresponds to an error event, provide instructions to a user via the external user device.

12. The electronic device of claim 11, wherein the processor is further operable to perform a calibration process to synchronize operations of the interface controller and the external user device.

13. The electronic device of claim 12, wherein said instructions are associated with altering an operating temperature of the electronic device.

14. An electronic device comprising:

an interface controller comprising;

a first interface coupled to a device external to the interface controller;

a second interface coupled to an external user device; and

a processor operable to;

test the first interface for compatibility with the device external to the interface controller during intermittent operation of the electronic device, said test comprising measuring a timing margin by which a timing error is avoided during the test in response to a determination that the error has not yet occurred during the test,

access stored data describing a physical layout of at least one device in response to an error received during said test and after said measuring of the timing margin, wherein the physical layout of the at least one device includes a physical layout of the interface controller,

determine, based on the accessed stored data, and without user input, whether the physical layout of the at least one device caused the error,

provide a result of the test to the external user device via the second interface, wherein said result of the test comprises a set of events and a corresponding set of timing margins of the device external to the interface controller and the first interface.