Method, system, and program product to implement C-routing for double pattern lithography

• US 8,560,998 B1
• Filed: 12/29/2010
• Issued: 10/15/2013
• Est. Priority Date: 12/29/2010
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Salowe, Jeffrey Scott, Raj, Satish Samuel
• Primary Examiner(s): DO, THUAN V
• Application Number:
  US12/981,431
• Time in Patent Office: 1,021 Days
• Field of Search: 716/55, 716/126, 716/139
• US Class Current: 716/126
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

Disclosed are a method, apparatus, and computer program product to implement routing for double patterning lithography. A three-phase routing scheme is employed, comprising a global router, a C-router, and a detail router. The C-router provides double patterning color seeding for shapes on routing tracks in the electronic design. The detail router employs space-tiles to perform double-patterning based routing for wires in the electronic design.

Claims

1. A computer implemented method for routing an electronic circuit design, the method implemented with a processor, the method comprising:

performing global routing for the electronic design to generate a high-level routing for the electronic design;

using a processor to perform C-routing for the electronic design using the high-level routing generated from the global routing, wherein

the C-routing provides color seeding for spacetiles in one or more conduits using a marking including a first color and a second color, in which a spacetile comprises a region that provides an allowable area for introducing one or more routing paths, and

the first color corresponds to a first manufacturing pattern mask and the second color corresponds to a second manufacturing pattern mask; and

performing detail routing based at least in part upon one or more color-seeded spacetiles from the C-routing.

2. The method of claim 1 in which the C-routing perform conduit routing or corridor routing.

3. The method of claim 1 in which track shapes are colored to perform double patterning lithography.

4. The method of claim 1 in which track assignments are made in consideration of spacing requirements.

5. The method of claim 4 in which the spacing requirements comprise spacing between shapes of the same color and spacing between shapes of different colors.

6. The method of claim 1 in which track assignments are made with spacing that matches pitch requirements for double pattern lithography.

7. The method of claim 1 in which track assignments do not correspond to a routing grid.

8. A computer program product embodied on a non-transitory computer usable medium, the non-transitory computer readable medium having stored thereon a sequence of instructions which, when executed by a processor causes the processor to execute a method for routing an electronic circuit design, the method comprising:

performing global routing for the electronic design to generate a high-level routing for the electronic design;

using a processor to perform C-routing for the electronic design using the high-level routing generated from the global routing, wherein

the C-routing provides color seeding for spacetiles in conduits using a marking including a first color and a second color, in which a spacetile comprises a region that provides an allowable area for introducing one or more routing paths, and

the first color corresponds to a first manufacturing pattern mask and the second color corresponds to a second manufacturing pattern mask; and

performing detail routing based at least in part upon one or more color-seeded spacetiles from the C-routing.

9. The computer program product of claim 8 in which the C-routing perform conduit routing or corridor routing.

10. The computer program product of claim 8 in which track shapes are colored to perform double patterning lithography.

11. The computer program product of claim 8 in which track assignments are made in consideration of spacing requirements.

12. The computer program product of claim 11 in which the spacing requirements comprise spacing between shapes of the same color and spacing between shapes of different colors.

13. The computer program product of claim 8 in which track assignments are made with spacing that matches pitch requirements for double pattern lithography.

14. The computer program product of claim 8 in which track assignments do not correspond to a routing grid.

15. A system for routing an electronic circuit design, comprising:

a processor;

a memory for holding programmable code, wherein the programmable code includes instructions which, when executed by the processor, causes the processor to;

perform global routing for the electronic design to generate a high-level routing for the electronic design,

perform C-routing for the electronic design using the high-level routing generated from the global routing, wherein

the C-routing provides color seeding for spacetiles in one or more conduits using a marking including a first color and a second color, in which a spacetile comprises a region that provides an allowable area for introducing one or more routing paths, and

the first color corresponds to a first manufacturing pattern mask and the second color corresponds to a second manufacturing pattern mask, and

perform detail routing based at least in part upon one or more color-seeded spacetiles from the C-routing.

16. The system of claim 15 in which the C-routing performs conduit routing or corridor routing.

17. The system of claim 15 in which track shapes are colored to perform double patterning lithography.

18. The system of claim 15 in which track assignments are made in consideration of spacing requirements.

19. The system of claim 18 in which the spacing requirements comprise spacing between shapes of the same color and spacing between shapes of different colors.

20. The system of claim 15 in which track assignments are made with spacing that matches pitch requirements for double pattern lithography.

21. The system of claim 15 in which track assignments do not correspond to a routing grid.