Compiler for generating an executable comprising instructions for a plurality of different instruction sets

• US 8,561,037 B2
• Filed: 08/29/2007
• Issued: 10/15/2013
• Est. Priority Date: 08/29/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Convey Computer (Micron Technology, Inc.)
• Inventors: Wallach, Steven J., Brewer, Tony
• Primary Examiner(s): Dao, Thuy
• Assistant Examiner(s): Smith, Cheneca
• Application Number:
  US11/847,169
• Publication Number:
  US 20090064095A1
• Time in Patent Office: 2,239 Days
• Field of Search: None
• US Class Current: 717/140
• CPC Class Codes: G06F 8/447 Target code generation

Abstract

A software compiler is provided that is operable for generating an executable that comprises instructions for a plurality of different instruction sets as may be employed by different processors in a multi-processor system. The compiler may generate an executable that includes a first portion of instructions to be processed by a first instruction set (such as a first instruction set of a first processor in a multi-processor system) and a second portion of instructions to be processed by a second instruction set (such as a second instruction set of a second processor in a multi-processor system). Such executable may be generated for execution on a multi-processor system that comprises at least one host processor, which may comprise a fixed instruction set, such as the well-known x86 instruction set, and at least one co-processor, which comprises dynamically reconfigurable logic that enables the co-processor'"'"'s instruction set to be dynamically reconfigured.

Claims

1. A method for compiling an executable file for execution on a target system, wherein the target system comprises a host processor having a first, fixed processor instruction set and a heterogeneous co-processor having reconfigurable logic for dynamically reconfiguring the co-processor'"'"'s instruction set to be any of a plurality of predefined co-processor instruction sets, wherein each of the plurality of predefined co-processor instruction sets provides extended instructions that are not natively supported by the first instruction set of the host processor, thereby extending the first processor instruction set of the host processor, and wherein the plurality of predefined co-processor instruction sets are mutually exclusive, the method comprising:

receiving, by a compiler, source code for a software application;

analyzing, by the compiler, types of operations encountered in the received source code

determining, by the compiler using said analyzing, instructions of a predefined co-processor instruction set of the plurality of predefined co-processor instruction sets that optimally enhance performance of at least a portion of the types of operations encountered in the received source code;

selecting, by the compiler, said predefined co-processor instruction set of said plurality of predefined co-processor instruction sets as a selected predefined co-processor instruction set having extended instructions to be generated in said executable file; and

processing, by the compiler, the source code to generate said executable file that comprises

native instructions of the host processor'"'"'s instruction set, and

extended instructions of said selected predefined co-processor instruction set determined to optimally enhance performance of the at least a portion of the types of operations encountered in the received source code.

2. The method of claim 1 further comprising:

determining, autonomously by the compiler using said analyzing, said selected predefined co-processor instruction set having extended instructions to be generated in said executable file.

3. The method of claim 2 wherein said determining comprises:

identifying, by said compiler, said selected predefined co-processor instruction set as a predefined co-processor instruction set of said plurality of predefined co-processor instruction sets having said instructions that optimally enhance performance of said at least a portion of the types of operations encountered in the received source code that said co-processor is to be configured to possess for execution of said executable file.

4. The method of claim 2 wherein said determining said selected predefined co-processor instruction set having extended instructions to be generated in said executable file comprises:

analyzing, by the compiler, the received source code for autonomously determining one of said plurality of predefined co-processor instruction sets.

5. The method of claim 4 wherein said analyzing comprises:

analyzing types of operations encountered in the source code; and

determining said selected predefined co-processor instruction set enhances performance of at least a portion of the types of operations encountered.

6. The method of claim 1 wherein said plurality of predefined co-processor instruction sets comprise at least one of the following:

a vector instruction set designed for efficiently processing 64-bit floating point operations;

a vector instruction set designed for efficiently processing 32-bit floating point operations; and

an instruction set designed for efficiently processing cryptography-related operations.

7. The method of claim 1 further comprising:

receiving, by the compiler, designation of one of said plurality of predefined co-processor instruction sets; and

determining, by the compiler using said designation, said selected predefined co-processor instruction set having extended instructions to be generated in said executable file.

8. The method of claim 7 wherein said designation is included in said source code.

9. The method of claim 7 wherein said receiving comprises:

receiving said designation from a user via a user interface of said compiler.

10. The method of claim 1 further comprising:

generating, within the executable file by the compiler, an identification of said selected predefined co-processor instruction set for which instructions are included in the executable file for use in determining that said selected predefined co-processor instruction set is loaded in said heterogeneous co-processor upon execution of said executable file.

11. The method of claim 1 further comprising:

performing, by a machine-independent optimizer of the compiler, optimizations to enhance performance of the executable file; and

wherein said determining said instructions of said predefined co-processor instruction set of the plurality of predefined co-processor instruction sets that optimally enhances performance of at least a portion of the types of operations encountered in the received source code is performed by a machine-dependent optimizer of the compiler.

12. The method of claim 1 wherein said compiler comprises computer-executable software code stored to a non-transitory, tangible computer-readable storage medium.

13. The method of claim 1 wherein said compiler comprises a plurality of code generators for generating said native instructions and extended instructions in the executable file.

14. The method of claim 13 further comprising:

generating, by a first one of said plurality of code generators, said native instructions; and

generating, by at least a second one of said plurality of code generators, said extended instructions.

15. The method of claim 14 wherein the plurality of code generators comprise:

a corresponding code generator for each of the plurality of predefined co-processor instruction sets, wherein each of said corresponding code generator is operable to generate instructions for its respective predefined co-processor instruction set.

16. The method of claim 1 wherein said processing further comprises:

generating one or more instructions in the executable file to cause the host processor to unknowingly dispatch said extended instructions of the executable file to the co-processor as a result of executing one or more of said native instructions for writing the extended instructions to a designated portion of a memory accessible by said co-processor.

17. The method of claim 1 wherein said processing further comprises:

generating one or more instructions in the executable file to trick the host processor into unknowingly dispatching said extended instructions of the executable file to the co-processor.

18. A method comprising:

receiving, by a compiler, source code for a software application; and

processing, by the compiler, the source code to generate an executable file that comprises instructions for execution on a target system, said target system comprising a host processor having a first, fixed processor instruction set and a heterogeneous co-processor having reconfigurable logic for dynamically reconfiguring the co-processor'"'"'s instruction set to be any of a plurality of predefined co-processor instruction sets, wherein each of the plurality of predefined co-processor instruction sets provides extended instructions that are not natively supported by the first instruction set of the host processor, thereby extending the first processor instruction set of the host processor, and wherein the plurality of predefined co-processor instruction sets are mutually exclusive, wherein the processing, by the compiler, includes;

analyzing types of operations encountered in the received source code

determining, using said analyzing, instructions of a predefined co-processor instruction set of the plurality of predefined co-processor instruction sets that optimally enhance performance of at least a portion of the types of operations encountered in the received source code;

selecting said predefined co-processor instruction set of said plurality of predefined co-processor instruction sets as a predefined co-processor instruction set having extended instructions to be generated in said executable file; and

generating said executable file, wherein instructions generated by the compiler in the executable file comprise instructions native to said first processor instruction set of the host processor and extended instructions of said selected predefined co-processor instruction set determined to optimally enhance performance of the at least a portion of the types of operations encountered in the received source code.

19. The method of claim 18 wherein said selecting comprises:

selecting, by said compiler, said predefined co-processor instruction set of said plurality of predefined co-processor instruction sets as an instruction set that said co-processor is to be configured to possess for execution of said executable file.

20. The method of claim 19 wherein the processing, by the compiler, further includes:

generating, within the executable file, an identification of the selected predefined co-processor instruction set.

21. The method of claim 18 wherein said plurality of predefined co-processor instruction sets comprise at least one of the following:

a vector instruction set designed for efficiently processing 64-bit floating point operations;

a vector instruction set designed for efficiently processing 32-bit floating point operations; and

an instruction set designed for efficiently processing cryptography-related operations.

22. The method of claim 18 further comprising:

performing, by a machine-independent optimizer of the compiler, optimizations to enhance performance of the executable file; and

wherein said determining said instructions of said predefined co-processor instruction set of the plurality of predefined co-processor instruction sets that optimally enhances performance of at least a portion of the types of operations encountered in the received source code is performed by a machine-dependent optimizer of the compiler.

23. The method of claim 18 wherein said compiler comprises computer-executable software code stored to a non-transitory, tangible computer-readable storage medium.

24. The method of claim 18 wherein said compiler comprises a plurality of code generators for generating said instructions native to said first processor instruction set of the host processor and said extended instructions in the executable file.

25. The method of claim 24 further comprising:

generating, by a first one of said plurality of code generators, said instructions native to said first processor instruction set of the host processor; and

generating, by at least a second one of said plurality of code generators, said extended instructions.

26. The method of claim 25 wherein the plurality of code generators comprise:

a corresponding code generator for each of the plurality of predefined co-processor instruction sets, wherein each of said corresponding code generator is operable to generate instructions for its respective predefined co-processor instruction set.

27. The method of claim 18 wherein said processing further comprises:

generating one or more instructions in the executable file to cause the host processor to unknowingly dispatch said extended instructions of the executable file to the co-processor as a result of executing one or more of said instructions that are native to said first processor instruction set of the host processor for writing the extended instructions to a designated portion of a memory accessible by said co-processor.

28. The method of claim 18 wherein said processing further comprises:

generating one or more instructions in the executable file to trick the host processor into unknowingly dispatching said extended instructions of the executable file to the co-processor.

29. A compiler comprising computer-executable software code stored to a non-transitory, tangible computer-readable storage medium, the compiler comprising:

front-end for receiving source code for a software application;

machine-dependent optimizer for determining instructions of a predefined co-processor instruction set of said plurality of predefined co-processor instruction sets that optimally enhance performance of operations in the received source code and thus for which extended instructions are to be generated from said received source code;

a plurality of code generators for processing the source code to generate instructions in an executable file for execution on a target system, said target system comprising a host processor having a first, fixed processor instruction set and a heterogeneous co-processor having reconfigurable logic for dynamically reconfiguring the co-processor'"'"'s instruction set to be any predefined co-processor instruction set of said plurality of predefined co-processor instruction sets, wherein each of the plurality of predefined co-processor instruction sets provides extended instructions that are not natively supported by the first instruction set of the host processor, thereby extending the first processor instruction set of the host processor, and wherein the plurality of predefined co-processor instruction sets are mutually exclusive;

wherein the instructions in the executable file comprise instructions that are native to the processor instruction set of the host processor and the extended instructions of predefined co-processor instruction set determined to be generated from said received source code by said machine-dependent optimizer; and

wherein the plurality of code generators comprise

a first code generator for generating said instructions that are native to the processor instruction set of the host processor, and

a plurality of second code generators, wherein the plurality of second code generators include a second code generator for generating said extended instructions of said predefined co-processor instruction set determined to optimally enhance performance of operations in the received source code.

30. The compiler of claim 29 further comprising:

machine-independent optimizer for performing optimizations to enhance performance of the executable file.

31. The compiler of claim 30 wherein said optimizations comprise at least one of strength reduction and common sub-expression elimination.

32. The compiler of claim 29 wherein said machine-dependent optimizer further determines said predefined co-processor instruction set of said plurality of predefined co-processor instruction sets for which extended instructions are to be generated for inclusion in said executable file.

33. The compiler of claim 29, wherein the compiler is further operable to generate, within the executable file, an identification of the predefined co-processor instruction set of the plurality of predefined co-processor instruction sets for which extended instructions are included in the executable file.

34. The compiler of claim 29 wherein the front-end is operable for receiving said source code coded in any of a plurality of different source code languages and generate an internal representation of the source for processing within the compiler.

35. The compiler of claim 29 wherein the plurality of second code generators comprise:

a corresponding code generator for each of the plurality of predefined co-processor instruction sets, wherein each of said corresponding code generator is operable to generate instructions for its respective predefined co-processor instruction set.

36. The compiler of claim 29 wherein said code generators generate one or more instructions in the executable file to cause the host processor to unknowingly dispatch said extended instructions of the executable file to the co-processor as a result of executing one or more instructions that are native to the processor instruction set of the host processor for writing the extended instructions to a designated portion of a memory accessible by said co-processor.

37. The compiler of claim 29 wherein said code generators generate one or more instructions in the executable file to trick the host processor into unknowingly dispatching said extended instructions of the executable file to the co-processor.