Creating a thread of execution in a computer processor without operating system intervention

• US 8,561,070 B2
• Filed: 12/02/2010
• Issued: 10/15/2013
• Est. Priority Date: 12/02/2010
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bohrer, Patrick J., Gheith, Ahmed, Peterson, James L.
• Primary Examiner(s): NGUYEN, VAN H
• Application Number:
  US12/959,075
• Publication Number:
  US 20120144396A1
• Time in Patent Office: 1,048 Days
• Field of Search: 718/100, 718/102
• US Class Current: 718/100
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system

Abstract

Creating a thread of execution in a computer processor includes an apparatus for copying data from a first set of registers to a second set of registers. The first set of registers is associated with a parent hardware thread and the second set of registers is associated with a child hardware thread. The copying is indicated by a hardware processor opcode called by a user-level process. The copying is performed with no operating system involvement. The child hardware thread is in a wait state. Creating the thread also includes changing, as indicated by the hardware processor opcode, the child hardware thread from the wait state to an ephemeral run state. The ephemeral run state indicates a lack of operating system support structures for the child hardware thread.

Claims

1. An apparatus for creating a thread of execution in a computer processor, the apparatus comprising a computer processor, a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the computer processor, cause the computer processor to:

copy, as indicated by a hardware processor opcode, the hardware processor opcode having been specified by a user-level process, data from a first set of registers to a second set of registers, wherein the first set of registers is associated with a parent hardware thread, wherein the second set of registers is associated with a child hardware thread, wherein the first set of registers and the second set of registers are located on the computer processor, wherein the child hardware thread is in a wait state; and

change, as indicated by the hardware processor opcode, the child hardware thread from the wait state to an ephemeral run state, wherein the ephemeral run state indicates a lack of operating system support structures for the child hardware thread.

2. The apparatus of claim 1 further comprising computer program instructions that, when executed by the computer processor, cause the computer processor to:

call, by the child hardware thread, an operating system function; and

create, by the operating system, a canonical operating system thread descriptor for the child hardware thread.

3. The apparatus of claim 1 further comprising computer program instructions that, when executed by the computer processor, cause the computer processor to:

receive, by the computer processor, an asynchronous interrupt of the child hardware thread thereby invoking an interrupt handler of the operating system; and

create, by the operating system, a canonical operating system thread descriptor for the child hardware thread.

4. The apparatus of claim 1 further comprising computer program instructions that, when executed by the computer processor, cause the computer processor to:

generate, by the child hardware thread, an execution exception that invokes an interrupt handler of the operating system; and

create, by the operating system, a canonical operating system thread descriptor for the child hardware thread.

5. The apparatus of claim 1 wherein the hardware processor opcode further comprises an operand specifying a maximum number of child hardware threads to change from the wait state to the ephemeral run state, and the apparatus further comprises computer program instructions that, when executed by the computer processor, cause the computer processor to return, as indicated by the hardware processor opcode to the user-level process, a number of child hardware threads changed from the wait state to the ephemeral run state.

6. The apparatus of claim 1 further comprising computer program instructions that, when executed by the computer processor, cause the computer processor to set, as indicated by the hardware processor opcode for the parent hardware thread, a flag indicating whether any child hardware threads were changed from the wait state to the ephemeral run state.

7. The apparatus of claim 1 further comprising computer program instructions that, when executed by the computer processor, cause the computer processor to set, as indicated by the hardware processor opcode for the parent hardware thread, a flag identifying the parent hardware thread as a parent.

8. A computer program product for creating a thread of execution in a computer processor, the computer program product disposed upon a non-transitory computer readable storage medium, the computer program product comprising computer program instructions to:

copy, as indicated by a hardware processor opcode, the hardware processor opcode having been specified by a user-level process, data from a first set of registers to a second set of registers, wherein the first set of registers is associated with a parent hardware thread, wherein the second set of registers is associated with a child hardware thread, wherein the first set of registers and the second set of registers are located on the computer processor, wherein the child hardware thread is in a wait state; and

change, as indicated by the hardware processor opcode, the child hardware thread from the wait state to an ephemeral run state, wherein an the ephemeral run state indicates a lack of operating system support structures for the child hardware thread.

9. The computer program product of claim 8 further comprising computer program instructions to:

call, by the child hardware thread, an operating system function; and

create, by the operating system, a canonical operating system thread descriptor for the child hardware thread.

10. The computer program product of claim 8 further comprising computer program instructions to:

receive, by the computer processor, an asynchronous interrupt of the child hardware thread thereby invoking an interrupt handler of the operating system; and

create, by the operating system, a canonical operating system thread descriptor for the child hardware thread.

11. The computer program product of claim 8 further comprising computer program instructions to:

generate, by the child hardware thread, an execution exception thereby invoking an interrupt handler of the operating system; and

create, by the operating system, a canonical operating system thread descriptor for the child hardware thread.

12. The computer program product of claim 8 wherein the hardware processor opcode further comprises an operand specifying a maximum number of child hardware threads to change from the wait state to the ephemeral run state, and the apparatus further comprises computer program instructions to return, as indicated by the hardware processor opcode to the user-level process, a number of child hardware threads changed from the wait state to the ephemeral run state.

13. The computer program product of claim 8 further comprising computer program instructions to set, as indicated by the hardware processor opcode for the parent hardware thread, a flag indicating whether any child hardware threads were changed from the wait state to the ephemeral run state.

14. The computer program product of claim 8 further comprising computer program instructions to set, as indicated by the hardware processor opcode for the parent hardware thread, a flag identifying the parent hardware thread as a parent.