Method for forming thin film resistor and terminal bond pad simultaneously

• US 8,563,336 B2
• Filed: 12/23/2008
• Issued: 10/22/2013
• Est. Priority Date: 12/23/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: International Business Machines Corporation
• Inventors: Chen, Fen, Gambino, Jeffrey P., He, Zhong-Xiang, Lee, Tom C., Malinowski, John C., Stamper, Anthony K.
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): DUONG, KHANH B
• Application Number:
  US12/342,430
• Publication Number:
  US 20100155893A1
• Time in Patent Office: 1,764 Days
• Field of Search: None
• US Class Current: 438/21
• CPC Class Codes: H01C 17/075 by thin film techniques H01C17/20 takes precedence
• CPC Class Codes: H01C 7/006 Thin film resistors
• CPC Class Codes: H01L 21/7685 the layer covering a conductive structure H01L21/76849 takes precedence
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05546 Dual damascene structure
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 28/24 with an active material comprising a refractory, transition or noble metal, metal compound or metal alloy, e.g. silicides, oxides, nitrides
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01016 : Sulfur [S]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

Disclosed are methods for forming a thin film resistor and terminal bond pad simultaneously. A method includes simultaneously forming a terminal bond pad on a terminal wire and a thin film resistor on two other wires.

Claims

1. A method of forming a semiconductor structure, comprising:

simultaneously forming a terminal bond pad on a terminal wire and a thin film resistor on two other wires, wherein the simultaneously forming comprises depositing a film and performing a single masking and etching of the deposited film; and

forming a cap over a high current wire simultaneously with the terminal bond pad and the thin film resistor, wherein the cap reduces electromigration effects in the high current wire.

2. A method of forming a semiconductor structure, comprising:

simultaneously forming a terminal bond pad on and directly contacting a terminal wire and a thin film resistor on two other wires; and

forming a pad film on the terminal bond pad,

wherein the terminal wire is over a substrate,

the terminal bond pad is over the terminal wire, and

the pad film is an electrically conductive material and is configured to be connected to a wire bond or controlled collapse chip connection (C4) solder ball attachment.

3. The method of claim 2, wherein the semiconductor structure is devoid of a terminal metal (TD) aluminum pad structure.

4. A method of forming a semiconductor structure, comprising:

simultaneously forming a terminal bond pad on and directly contacting a terminal wire and a thin film resistor on two other wires; and

forming a pad film on the terminal bond pad,

wherein the terminal wire is over a substrate,

the terminal bond pad is over the terminal wire, and

the forming the pad film comprises;

depositing a pad film layer over substantially all exposed upper surfaces of the semiconductor structure;

photolithographic masking the pad film layer; and

etching away portions of the pad film layer to form the pad film.

5. A method of forming a semiconductor structure, comprising:

simultaneously forming a terminal bond pad on and directly contacting a terminal wire and a thin film resistor on two other wires; and

forming a pad film on the terminal bond pad,

wherein the terminal wire is over a substrate,

the terminal bond pad is over the terminal wire, and

the forming the pad film comprises;

forming photoresist over selected exposed upper surfaces of the semiconductor structure, leaving at least a portion of the terminal bond pad exposed;

depositing a pad film layer over the photoresist and the exposed portion of the terminal bond pad; and

lifting off the photoresist.

6. A method of forming a semiconductor structure, comprising:

simultaneously forming a terminal bond pad on and directly contacting a terminal wire and a thin film resistor on two other wires; and

forming a pad film on the terminal bond pad,

wherein the terminal wire is over a substrate,

the terminal bond pad is over the terminal wire, and

the forming the pad film comprises fabricating the pad film on the terminal bond pad using damascene processes.

7. A method of forming a semiconductor structure, comprising:

forming a diffusion barrier capping layer on an uppermost wiring level in which a plurality of wires are formed;

forming an isolation layer on the diffusion barrier capping layer;

forming openings in the diffusion barrier capping layer and the isolation layer over the plurality of wires;

forming a layer of refractory metal in the openings and on exposed upper surfaces of the isolation layer and the plurality of wires; and

removing portions of the layer of refractory metal while leaving other portions of the layer of refractory metal in the openings and on the plurality of wires.

8. The method of claim 7, wherein:

the plurality of wires comprises a terminal wire, two related wires, and another wire, and

the removing portions of the layer of refractory metal while leaving other portions of the layer of refractory metal in the openings and on the plurality of wires simultaneously forms;

a terminal bond pad on the terminal wire, a thin film resistor between the two related wires, and a cap on the other wire.

9. The method of claim 8, wherein:

the forming openings in the diffusion barrier capping layer and the isolation layer comprises removing portions of the diffusion barrier capping layer and the isolation layer between the two related wires; and

the forming the layer of refractory metal comprises depositing the refractory metal on the uppermost wiring level between the two related wires.

10. The method of claim 8, further comprising forming a terminal pad film on the terminal bond pad.

11. A method of forming a semiconductor device, comprising:

simultaneously forming a thin film resistor and a refractory metal cap over a lower wire, wherein the lower wire is in an intermediate wiring level (n) and the refractory metal cap directly contacts the lower wire, and wherein the simultaneously forming the thin film resistor and the refractory metal cap comprises depositing a resistor film and performing a single masking and etching of the deposited resistor film;

forming a next wiring level (n+1) over the thin film resistor and the cap;

forming at least one of a diffusion barrier capping layer and an isolation layer between the intermediate wiring level (n) and the next wiring level (n+1);

forming an upper wire in the next wiring level (n+1) conductively connected to the cap; and

forming two related wires in the next wiring level (n+1) conductively connected to the thin film resistor.

12. The method of claim 11, wherein the thin film resistor and the refractory metal cap comprise portions of a common layer of refractory metal.

13. The method of claim 12, wherein the refractory metal comprises tantalum nitride (TaN).

14. The method of claim 11, further comprising:

forming a first via between the upper wire and the cap;

forming a second via between a first one of the two related wires and the thin film resistor; and

forming a third via between a second one of the two related wires and the thin film resistor.

15. A method of forming a semiconductor device, comprising:

simultaneously forming a thin film resistor and a refractory metal cap over a lower wire, wherein the lower wire is in an intermediate wiring level (n);

forming a next wiring level (n+1) over the thin film resistor and the cap;

forming an upper wire in the next wiring level (n+1) conductively connected to the cap; and

forming two related wires in the next wiring level (n+1) conductively connected to the thin film resistor,

wherein the simultaneously forming comprises;

patterning a barrier layer to expose a portion of the lower wire, wherein the barrier layer includes at least one of a diffusion barrier layer and an isolation oxide layer;

forming a layer of refractory metal on the portion of the lower wire and the barrier layer; and

selectively removing portions of the layer of refractory metal to form the thin film resistor and the cap.

16. A method of forming a semiconductor device, comprising:

forming a lower wire in a dielectric material;

forming an insulator on the lower wire and the dielectric material;

removing a portion of the insulator to expose a portion of the lower wire;

simultaneously forming a thin film resistor on the insulator and a refractory metal cap directly contacting the portion of the lower wire;

forming a dielectric film on the thin film resistor and the cap;

forming an upper wire in the dielectric film conductively connected to the cap; and

forming two related wires in the dielectric film conductively connected to the thin film resistor.