Trench-based power semiconductor devices with increased breakdown voltage characteristics

• US 8,563,377 B2
• Filed: 04/11/2012
• Issued: 10/22/2013
• Est. Priority Date: 12/08/2008
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Yedinak, Joseph A., Calafut, Daniel, Probst, Dean E.
• Primary Examiner(s): Lee, Kyoung
• Application Number:
  US13/443,986
• Publication Number:
  US 20120193748A1
• Time in Patent Office: 559 Days
• Field of Search: None
• US Class Current: 438/259
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/0611 for increasing or controlling the breakdown voltage of reverse biased devices H01L29/0661 takes precedence
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

Claims

1. A semiconductor device comprising:

a first trench disposed in a semiconductor region and aligned along a first direction from an end of the first trench disposed in a connection region to a portion of the first trench disposed in an active region, the first trench having;

a dielectric layer lining a sidewall of the first trench, and

a shield electrode disposed in the first trench,

a second trench disposed in the semiconductor region and aligned parallel to the first trench, the second trench having;

a dielectric layer lining a sidewall of the second trench, and

a shield electrode disposed in the second trench;

a first well region of a first conductivity type having at least a portion disposed in the active region and extending between the sidewall of the first trench and the sidewall of the second trench along a second direction orthogonal to the first direction, the first well region having an end in the connection region; and

a second well region of the first conductivity type and having a doping concentration lower than a doping concentration of the first well region, the second well region extending between the sidewall of the first trench and the sidewall of the second trench along the second direction, and extending along the first direction from the end of the first trench to the end of the first well region.

2. The semiconductor device of claim 1, further comprising:

a conductive layer electrically coupled with the first well region such that a potential applied to the conductive layer is provided to the first well region.

3. The semiconductor device of claim 1, wherein the end of the first trench is a distance from the end of the first well region, the first trench extends to a depth into the semiconductor region substantially equal to the distance.

4. The semiconductor device of claim 1, wherein:

the end of the first trench is a distance from the end of the first well region,

the first trench extends to a first depth into the semiconductor region, and

the first well region extends to a second depth into the semiconductor region, the second depth being less than the first depth, the distance being substantially equal to a difference between the first depth and the second depth.

5. The semiconductor device of claim 1, wherein:

the semiconductor region is disposed on a semiconductor die, and

the end of the first trench is parallel with an edge of the semiconductor die, a portion of the semiconductor region is disposed between the end of the first trench and the edge of the semiconductor die, the portion of the semiconductor region is excluded from a termination trench.

6. The semiconductor device of claim 1, further comprising:

a field plate disposed over the end of the first well region, the field plate being electrically coupled to the shield electrode disposed in the first trench and the shield electrode disposed in the second trench.

7. The semiconductor device of claim 1, wherein layers of the semiconductor device that are disposed over the end of the first well region are electrically isolated from the shield electrode disposed in the first trench and isolated from the shield electrode disposed in the second trench.

8. A method of forming a semiconductor device, the method comprising:

forming a first trench in a semiconductor region and aligned along a first direction from an end of the first trench disposed in a connection region to a portion of the first trench disposed in an active region;

forming a dielectric layer disposed on a sidewall of the first trench;

forming a shield electrode disposed within the first trench and disposed within the dielectric layer disposed on the sidewall of the first trench;

forming a second trench in the semiconductor region and aligned parallel to the first trench;

forming a dielectric layer disposed on a sidewall of the second trench;

forming a shield electrode disposed within the second trench and disposed within the dielectric layer disposed on the sidewall of the second trench;

forming a first well region of a first conductivity type having at least a portion, disposed in the active region and extending between sidewall of the first trench and the sidewall of the second trench along a second direction orthogonal to the first direction, the first well region having an end in the connection region; and

forming a second well region of the first conductivity type and having a doping concentration lower than a doping concentration of the first well region, the second well region extending between the sidewall of the first trench and the sidewall of the second trench along the second direction and extending along the first direction from the end of the first trench to the end of the first well region.

9. The method of claim 8, further comprising:

forming a conductive layer electrically coupled with the first well region such that a potential applied to the conductive layer is provided to the first well region.

10. The method of claim 8, wherein the end of the first trench is a distance from the end of the first well region, the first trench extends to a depth into the semiconductor region substantially equal to the distance.

11. The method of claim 8 wherein:

the end of the first trench is a distance from the end of the first well region,

the first trench is formed to extend to a first depth into the semiconductor region, and

the first well region is formed to extend to a second depth into the semiconductor region, the second depth being less than the first depth, the distance being substantially equal to a difference between the first depth and the second depth.

12. The method of claim 8, further comprising:

forming an epitaxial layer including the semiconductor region, the semiconductor region being disposed on a semiconductor die, the end of the first trench being parallel with an edge of the semiconductor die such that a portion of the semiconductor region is disposed between the end of the first trench and the edge of the semiconductor die, the portion of the semiconductor region being excluded from a termination trench.

13. The method of claim 8, further comprising forming a field plate disposed over the end of the first well region, the field plate being electrically coupled to the shield electrode disposed in the first trench and coupled to the shield electrode disposed in the second trench.

14. The method of claim 8, further comprising at least one layer disposed over the end of the first well region, the at least one layer being electrically isolated from the shield electrode disposed in the first trench and coupled to the shield electrode disposed in the second trench.

15. A semiconductor device comprising:

an epitaxial layer of a first conductivity type, the epitaxial layer being formed on a semiconductor die;

a first gate trench formed in the epitaxial layer, the first gate trench having a proximal end and a distal end;

a second gate trench formed in the epitaxial layer, the second gate trench having a proximal end and a distal end;

a mesa region disposed between the first gate trench and the second gate trench;

a first well region of a second conductivity type disposed in the mesa region, a proximal end of the first well region being spaced from the proximal end of the first gate trench in a direction toward the distal end of the first gate trench; and

a second well region of the second conductivity type disposed in the mesa region, the second well region extending from the proximal end of the first gate trench to the proximal end of the first well region and having a doping concentration that is different than a doping concentration of the first well region.

16. The semiconductor device of claim 15, wherein the doping concentration of the second well region is lower than the doping concentration of the first well region.

17. The semiconductor device of claim 15, wherein:

the proximal end of the first gate trench is co-linear with the proximal end of the second gate trench, and

the distal end of the first gate trench is co-linear with the distal end of the second gate trench.

18. The semiconductor device of claim 15, wherein a distal end of the first well region is spaced from the distal end of the first gate trench in a direction toward the proximal end of the first gate trench, the semiconductor device further comprising:

a third well region of the second conductivity type disposed in the mesa region, the third well region extending from the distal end of the first gate trench to the distal end of the first well region and having a doping concentration that is substantially the same as the doping concentration of the second well region.

19. The semiconductor device of claim 15, wherein the first gate trench includes:

a first dielectric layer disposed on a sidewall of the first gate trench;

a shield electrode disposed in a lower portion of the first gate trench and disposed within the first dielectric layer;

a second dielectric layer disposed on the shield electrode; and

a gate electrode disposed on the second dielectric layer.