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Three dimensional integrated circuit integration using alignment via/dielectric bonding first and through via formation last

  • US 8,563,403 B1
  • Filed: 06/27/2012
  • Issued: 10/22/2013
  • Est. Priority Date: 06/27/2012
  • Status: Active Grant
First Claim
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1. A method, comprising:

  • forming a first integrated circuit (IC) device having a first substrate, an alignment via defined in the first substrate, a first wiring layer over the alignment via, and a first bonding layer over the first wiring layer;

    forming a second IC device having a second substrate, a second wiring layer over the second substrate, and a second bonding layer over the second wiring layer;

    bonding the first bonding layer of first IC device to the second bonding layer of second IC device;

    thinning a backside of the first IC device so as to expose the alignment via; and

    using the exposed alignment via to form a deep, through substrate via (TSV) that passes through the first IC device, through a bonding interface between the first IC device and second IC device, and landing on the second wiring layer of the second IC device.

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