Three dimensional integrated circuit integration using alignment via/dielectric bonding first and through via formation last

• US 8,563,403 B1
• Filed: 06/27/2012
• Issued: 10/22/2013
• Est. Priority Date: 06/27/2012
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Farooq, Mukta G., Skordas, Spyridon, Volant, Richard P., Winstel, Kevin R.
• Primary Examiner(s): Blum, David S
• Application Number:
  US13/534,067
• Time in Patent Office: 482 Days
• Field of Search: 438/224, 438/387, 438/455, 438/459, 438/559, 438/667, 257/E21.597, 257/E21.677, 257/E23.011
• US Class Current: 438/459
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05078 being disposed next to each other, e.g. side-to-side arrangements
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/08146 the bonding area connecting to a via connection in the body
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/80 Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2224/80006 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/80129 Shape or position of the other item
• CPC Class Codes: H01L 2224/80345 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/80896 between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/8203 Reshaping, e.g. forming vias
• CPC Class Codes: H01L 2224/821 Forming a build-up interconnect
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/83005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/8313 : using marks formed on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/8385 : using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/9202 : Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/9212 : Sequential connecting processes
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06593 : Mounting aids permanently on device; arrangements for alignment
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/1461 : MEMS

Abstract

A method includes forming a first integrated circuit (IC) device having a first substrate, an alignment via defined in the first substrate, a first wiring layer over the alignment via, and a first bonding layer over the first wiring layer; forming a second IC device having a second substrate, a second wiring layer over the second substrate, and a second bonding layer over the second wiring layer; bonding the first bonding layer of first IC device to the second bonding layer of second IC device; thinning a backside of the first IC device so as to expose the alignment via; and using the exposed alignment via to form a deep, through substrate via (TSV) that passes through the first IC device, through a bonding interface between the first IC device and second IC device, and landing on the second wiring layer of the second IC device.

Claims

1. A method, comprising:

forming a first integrated circuit (IC) device having a first substrate, an alignment via defined in the first substrate, a first wiring layer over the alignment via, and a first bonding layer over the first wiring layer;

forming a second IC device having a second substrate, a second wiring layer over the second substrate, and a second bonding layer over the second wiring layer;

bonding the first bonding layer of first IC device to the second bonding layer of second IC device;

thinning a backside of the first IC device so as to expose the alignment via; and

using the exposed alignment via to form a deep, through substrate via (TSV) that passes through the first IC device, through a bonding interface between the first IC device and second IC device, and landing on the second wiring layer of the second IC device.

2. The method of claim 1, further comprising electrically connecting the deep TSV to the alignment via, thereby establishing electrical communication between the first and second IC devices.

3. The method of claim 1, wherein thinning the backside of the first IC device further comprises etching silicon until an insulating portion of a liner of the alignment via is exposed.

4. The method of claim 3, further comprising depositing an insulating film stack over the backside of the first IC device and exposed insulating portion of the liner of the alignment via.

5. The method of claim 4, further comprising planarizing the insulating film stack until a conductive portion of the alignment via is exposed.

6. The method of claim 5, further comprising forming a first cap layer over the insulating film stack and the exposed conductive portion of the alignment via.

7. The method of claim 6, wherein the deep TSV is formed through the first cap layer, using the alignment via.

8. The method of claim 7, further comprising planarizing the first cap layer so as to expose both the conductive portion of the alignment via and a conductive portion of the deep TSV.

9. The method of claim 8, further comprising forming a second cap layer over the deep TSV and the alignment via.

10. The method of claim 9, further comprising forming a dielectric layer over the second cap layer, the deep TSV and the alignment via, patterning the dielectric layer, and forming a conductive strap within the dielectric layer that electrically connects the deep TSV and the alignment via.

11. The method of claim 1, wherein bonding the first IC device to the second IC device comprises face-to-face bonding.

12. The method of claim 1, wherein bonding the first IC device to the second IC device comprises face-to-back bonding.

13. A method, comprising:

forming an alignment via within a first integrated circuit (IC) device;

forming a 3D, bonded IC device by bonding the first IC device to a second IC device so as to define a first bonding interface therebetween;

thinning the 3D bonded IC device so as to expose the alignment via;

using the exposed alignment via to form a first set of vias that pass through the first IC device, through the first bonding interface and into the second IC device, and land on conductive pads located within the second IC device; and

forming a second set of vias within the first IC device that land on conductive pads located within the first IC device, and that do not pass through the first bonding interface.

14. The method of claim 13, further comprising filling the first and second sets of vias with a conductive material, and electrically connecting at least one via of the first set of vias to at least one via of the second set of vias, thereby establishing electrical communication between the first and second IC devices of the 3D bonded IC device.

15. The method of claim 14, wherein at least one of the second set of vias comprises the alignment via.

16. The method of claim 14, wherein the first bonding interface is formed by one or more of:

oxide-to-oxide bonding, permanent adhesive bonding, metal-to-metal thermal compression bonding, and combinations thereof.

17. The method of claim 14, further comprising:

forming a second alignment via within a third IC device;

bonding the third IC device to the 3D bonded IC device so as to define a second bonding interface therebetween;

thinning the 3D bonded IC device so as to expose the second alignment via;

using the exposed second alignment via to form a third set of vias that pass through the third IC device, through the second bonding interface and into the first IC device, and land on conductive pads located within the first IC device; and

forming a fourth set of vias within the third IC device that land on conductive pads located within the third IC device, and that do not pass through the second bonding interface; and

filling the third and fourth sets of vias with a conductive material, and electrically connecting at least one via of the third set of vias to at least one via of the fourth set of vias, thereby establishing electrical communication between the first, second and third IC devices of the 3D bonded IC device.

18. The method of claim 13, wherein the first IC device comprises an epitaxially grown semiconductor layer formed on a sacrificial base layer, and wherein the sacrificial base layer is removed subsequent to bonding the first and second IC devices, and prior to formation of the first and second sets of vias.

19. The method of claim 18, wherein the sacrificial base layer of the first IC device has a substantially higher dopant concentration with respect to the epitaxially grown semiconductor layer so as to create an etch selectivity therebetween.

20. The method of claim 17, wherein bonding of the first, second and third IC devices comprises one or more of:

face-to-face bonding, face-to-back bonding, and face-to-face-to-back bonding.