Semiconductor device

• US 8,563,973 B2
• Filed: 03/07/2011
• Issued: 10/22/2013
• Est. Priority Date: 03/19/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Inoue, Hiroki, Matsuzaki, Takanori, Nagatsuka, Shuhei
• Primary Examiner(s): MATTHEWS, COLLEEN ANN
• Application Number:
  US13/041,581
• Publication Number:
  US 20110227072A1
• Time in Patent Office: 960 Days
• Field of Search: 257/43, 257/E29.255
• US Class Current: 257/43
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A semiconductor device including a nonvolatile memory cell including a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor is provided. Data is written to the memory cell by turning on the writing transistor and supplying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected to each other, and then turning off the writing transistor so that a predetermined amount of charge is held at the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.

Claims

1. A semiconductor device including a memory cell, the memory cell comprising:

a first transistor;

a second transistor electrically connected to the first transistor; and

a capacitor,

wherein the first transistor is a p-channel type transistor and comprises a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region,

wherein the second transistor comprises a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region comprising an oxide semiconductor,

wherein the first gate electrode, one electrode of the capacitor and one of the second source electrode and the second drain electrode are electrically connected to one another and form a node where an electric charge is held, and

wherein the one electrode of the capacitor is the one of the second source electrode and the second drain electrode.

2. The semiconductor device according to claim 1, wherein the second transistor is an n-channel type transistor.

3. The semiconductor device according to claim 1, wherein the second transistor is overlapped with at least part of the first transistor.

4. The semiconductor device according to claim 1, wherein the first channel formation region comprises silicon.

5. A semiconductor device including a first wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring, and a memory cell connected between the first wiring and the second wiring,

wherein the memory cell comprises:

a first transistor comprising a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region;

a second transistor comprising a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region comprising an oxide semiconductor; and

a capacitor,

wherein the first transistor is a p-channel type transistor,

wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one electrode of the capacitor are electrically connected to one another and form a node where an electric charge is held,

wherein the one electrode of the capacitor is the one of the second source electrode and the second drain electrode,

wherein the first wiring and one of the first source electrode and the first drain electrode are electrically connected to each other,

wherein the second wiring and the other of the first source electrode and the first drain electrode are electrically connected to each other,

wherein the third wiring and the other of the second source electrode and the second drain electrode are electrically connected to each other,

wherein the fourth wiring and the second gate electrode are electrically connected to each other, and

wherein the fifth wiring and the other electrode of the capacitor are electrically connected to each other.

6. The semiconductor device according to claim 5, wherein the second transistor is an n-channel type transistor.

7. The semiconductor device according to claim 5, wherein the second transistor is overlapped with at least part of the first transistor.

8. The semiconductor device according to claim 5, wherein the first channel formation region comprises silicon.